WIPO logo
Mobile | Deutsch | Español | Français | 日本語 | 한국어 | Português | Русский | 中文 | العربية |
PATENTSCOPE

Search International and National Patent Collections
World Intellectual Property Organization
Options
Query Language
Stem
Sort by:
List Length
Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2018123659) METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND FILM FORMING APPARATUS
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/123659 International Application No.: PCT/JP2017/045126
Publication Date: 05.07.2018 International Filing Date: 15.12.2017
IPC:
H01L 21/365 (2006.01) ,H01L 21/205 (2006.01) ,H01L 21/336 (2006.01) ,H01L 29/786 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
34
the devices having semiconductor bodies not provided for in groups H01L21/06, H01L21/16, and H01L21/18159
36
Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
365
using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
20
Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
205
using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
Applicants: SHARP KABUSHIKI KAISHA[JP/JP]; 1, Takumi-cho, Sakai-ku, Sakai City, Osaka 5908522, JP
Inventors: NAKAJIMA Shinji; --
NISHIKI Hirohiko; --
MIMURA Hirohide; --
SAITOH Yuhichi; --
TAKEDA Yujiro; --
MURASHIGE Shogo; --
ISHIDA Izumi; --
OKABE Tohru; --
Agent: OKUDA Seiji; JP
Priority Data:
2016-25339227.12.2016JP
Title (EN) METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE AND FILM FORMING APPARATUS
(FR) PROCÉDÉ DE FABRICATION D'UN DISPOSITIF À SEMICONDUCTEUR ET APPAREIL DE FORMATION DE FILM
(JA) 半導体装置の製造方法および成膜装置
Abstract:
(EN) Provided is a method for manufacturing a semiconductor device, the semiconductor device comprising a substrate (1), and an oxide semiconductor TFT that is supported by the substrate (1) and includes an oxide semiconductor film as an active layer. The method comprises: a step (A) for preparing MO gas containing a first organometallic compound that contains In, and a second organometallic compound that contains Zn; and a step (B) for supplying gas containing MO gas and oxygen to the substrate (1) placed in a chamber, in a state where the substrate (1) is heated to 500°C or less, and growing an oxide semiconductor film (2A) that contains In and Zn on the substrate (1) by a MOCVD method. The step (B) is performed in a state where plasma (3) is formed in the chamber.
(FR) L'invention concerne un procédé de fabrication d'un dispositif à semiconducteur, le dispositif à semiconducteur comprenant un substrat (1), et un TFT à semiconducteur à oxyde qui est supporté par le substrat (1) et comprenant un film d'oxyde semiconducteur en tant que couche active. Le procédé comprend : une étape (A) pour préparer un gaz MO contenant un premier composé organométallique qui contient de l'In, et un second composé organométallique qui contient du Zn; et une étape (B) pour fournir du gaz contenant du gaz MO et de l'oxygène au substrat (1) placé dans une chambre, dans un état dans lequel le substrat (1) est chauffé à 500 °C ou moins, et la croissance d'un film semiconducteur d'oxyde (2A) qui contient de l'In et du Zn sur le substrat (1) par un procédé MOCVD. L'étape (B) est effectuée dans un état dans lequel du plasma (3) est formé dans la chambre.
(JA) 半導体装置の製造方法は、基板(1)と、基板(1)に支持された、酸化物半導体膜を活性層とする酸化物半導体TFTとを備えた半導体装置の製造方法であって、(A)Inを含む第1の有機金属化合物、およびZnを含む第2の有機金属化合物を含むMOガスを用意する工程と、(B)チャンバー内に設置した基板(1)に、基板(1)を500℃以下の温度に加熱した状態で、MOガスおよび酸素を含むガスを供給し、基板(1)上にInおよびZnを含む酸化物半導体膜(2A)をMOCVD法により成長させる工程とを含み、工程(B)は、チャンバー内にプラズマ(3)を形成した状態で行われる。
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)