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1. (WO2018122894) METHOD FOR MANUFACTURING ELECTRONIC DEVICE, AND ELECTRONIC DEVICE
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Pub. No.: WO/2018/122894 International Application No.: PCT/JP2016/088619
Publication Date: 05.07.2018 International Filing Date: 26.12.2016
Chapter 2 Demand Filed: 15.03.2017
IPC:
H01L 23/28 (2006.01) ,H01L 21/56 (2006.01) ,H01L 23/34 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
28
Encapsulation, e.g. encapsulating layers, coatings
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
56
Encapsulations, e.g. encapsulating layers, coatings
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
34
Arrangements for cooling, heating, ventilating or temperature compensation
Applicants:
新電元工業株式会社 SHINDENGEN ELECTRIC MANUFACTURING CO., LTD. [JP/JP]; 東京都千代田区大手町二丁目2番1号 2-1, Ohtemachi 2-chome, Chiyoda-ku, Tokyo 1000004, JP
Inventors:
鎌田 英紀 KAMADA Hideki; JP
Agent:
大野 聖二 OHNO Seiji; JP
大野 浩之 OHNO Hiroyuki; JP
Priority Data:
Title (EN) METHOD FOR MANUFACTURING ELECTRONIC DEVICE, AND ELECTRONIC DEVICE
(FR) PROCÉDÉ DE FABRICATION DE DISPOSITIF ÉLECTRONIQUE, ET DISPOSITIF ÉLECTRONIQUE
(JA) 電子装置の製造方法及び電子装置
Abstract:
(EN) This method for manufacturing an electronic device has: a step for mounting a substrate 10, which has a metal plate 11 on the rear side thereof, on a rear-side die 110 which has a die recess 111; a step for positioning a front-side die 120 so as to cover the substrate 10; and a step for pouring a resin between the front-side die 100 and the rear-side die 110 while pressing the substrate 10 against the rear-side die 110. In the step for pouring the resin, the substrate 10 is pressed against the rear-side die 110 with the peripheral edges of the metal plate 11 abutting the edges of the die recess 111.
(FR) Ce procédé de fabrication d'un dispositif électronique comprend : une étape de montage d'un substrat 10, qui a une plaque métallique 11 sur son côté arrière, sur une puce côté arrière 110 qui a un évidement de puce 111 ; une étape de positionnement d'une puce côté avant 120 de manière à recouvrir le substrat 10 ; et une étape de versement d'une résine entre la puce côté avant 100 et la puce côté arrière 110 tout en pressant le substrat 10 contre la puce côté arrière 110. Lors de l'étape de versement de la résine, le substrat 10 est pressé contre la puce côté arrière 110, les bords périphériques de la plaque métallique 11 venant en butée contre les bords de l'évidement de puce 111.
(JA) 電子装置の製造方法は、金型凹部111を有する裏面側金型110に、裏面側に金属板11を有する基板10を載置する工程と、前記基板10を覆うようにしておもて面側金型120を位置づける工程と、前記基板10を前記裏面側金型110に押圧しながら、前記おもて面金型100と前記裏面側金型110との間に樹脂を流し込む工程と、を有している。前記樹脂を流し込む工程において、前記金属板11の周縁部が前記金型凹部111の縁に当接した状態で、前記基板10が前記裏面側金型110に押圧される。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)