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1. (WO2018122517) METHOD FOR PRODUCING AN OPTOELECTRONIC DEVICE COMPRISING A STEP OF ETCHING THE REAR FACE OF THE GROWTH SUBSTRATE
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Pub. No.: WO/2018/122517 International Application No.: PCT/FR2017/053817
Publication Date: 05.07.2018 International Filing Date: 22.12.2017
IPC:
H01L 33/00 (2010.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
Applicants:
ALEDIA [FR/FR]; Chez Minatec, Bâtiment Haute Technologie N°52 7 Parvis Louis Neel BP 50 38040 Grenoble, FR
Inventors:
POURQUIER, Eric; FR
Agent:
LE GOALLER, Christophe; FR
DUPONT, Jean-Baptiste; FR
COLOMBO, Michel; FR
Priority Data:
166340927.12.2016FR
Title (EN) METHOD FOR PRODUCING AN OPTOELECTRONIC DEVICE COMPRISING A STEP OF ETCHING THE REAR FACE OF THE GROWTH SUBSTRATE
(FR) PROCEDE DE REALISATION D'UN DISPOSITIF OPTOELECTRONIQUE COMPORTANT UNE ETAPE DE GRAVURE DE LA FACE ARRIERE DU SUBSTRAT DE CROISSANCE
Abstract:
(EN) The invention relates to a method for manufacturing an optoelectronic device (1), comprising the following steps: a) providing a growth substrate (10) made from a semiconductor material; b) forming a plurality of diodes (20) each comprising a lower face (20i); c) removing at least a portion (12; 13) of the substrate so as to free the lower face (20i); wherein: - step a) involves producing a lower part and an upper part of the substrate, the upper part (12) having a uniform thickness (eref) and a level of doping less than that of the lower part; - step c) involving removal of the lower part (11) by selective chemical etching with respect to the upper part (12).
(FR) L'invention porte sur un procédé de fabrication d'un dispositif optoélectronique (1), comportant les étapes suivantes : a) fournir un substrat (10) de croissance en un matériau semiconducteur; b) former une pluralité de diodes (20) comportant chacune une face inférieure (20i); c) supprimer au moins une portion (12; 13) du substrat de manière à rendre libre la face inférieure (20i); dans lequel : - l'étape a) comporte la réalisation d'une partie inférieure et d'une partie supérieure du substrat, la partie supérieure (12) présentant une épaisseur (eref) homogène et un niveau de dopage inférieur à celui de la partie inférieure; - l'étape c) comportant une suppression de la partie inférieure (11) par gravure chimique sélective vis-à-vis de la partie supérieure (12).
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: French (FR)
Filing Language: French (FR)