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1. (WO2018120997) ACTIVE ARRAY SUBSTRATE AND FABRICATION METHOD THEREFOR
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Pub. No.: WO/2018/120997 International Application No.: PCT/CN2017/106320
Publication Date: 05.07.2018 International Filing Date: 16.10.2017
IPC:
H01L 21/77 (2017.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
Applicants:
惠科股份有限公司 HKC CORPORATION LIMITED [CN/CN]; 中国广东省深圳市 宝安区石岩街道水田村民营工业园惠科工业园厂房1、2、3栋,九州阳光1号厂房5、7楼 5th and 7th Floor of Factory Building 1, Jiuzhou Yangguang Factory Buildings 1, 2, 3, HKC Industrial Park, Privately Operated Industrial Park Shuitian Village, Shiyan Sub-district, Baoan District Shenzhen, Guangdong 518000, CN
重庆惠科金渝光电科技有限公司 CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CO., LTD.; 中国重庆市 巴南区界石镇石景路1号 No.1 Shijing Rd., Jieshi, Banan District Chongqing 400000, CN
Inventors:
卓恩宗 CHO, En-Tsung; CN
Agent:
深圳市百瑞专利商标事务所(普通合伙) SHENZHEN BAIRUI PATENT & TRADEMARK OFFICE; 中国广东省深圳市 福田香蜜湖街道竹子林七路2号益华综合楼A栋第六层西01# West #01, 6F, Building A, Yihua Complex Building No.2, Zhuzilin Qi Rd, Xiangmihu St, Futian District Shenzhen, Guangdong 518000, CN
Priority Data:
201611270692.730.12.2016CN
Title (EN) ACTIVE ARRAY SUBSTRATE AND FABRICATION METHOD THEREFOR
(FR) SUBSTRAT DE RÉSEAU ACTIF ET SON PROCÉDÉ DE FABRICATION
(ZH) 主动阵列基板及其制造方法
Abstract:
(EN) An active array substrate and a fabrication method therefor, the fabrication method comprising: providing a substrate (10); forming a gate electrode on the substrate (10); sequentially forming a gate electrode insulation layer (22), a semiconductor layer and an ohmic contact layer (24) on a transparent substrate and the gate electrode; forming a source electrode (25) and a drain electrode (26) on the ohmic contact layer (24); forming a protective layer (30) on the source electrode (25) and the drain electrode (26); forming a pixel electrode layer (50) on the protective layer (30), wherein the pixel electrode layer (50) is electrically connected to the drain electrode (26); the gate electrode insulation layer (22) comprises nano-porous silicon and nano-particles, the dielectric constant of the nano-particles being greater than the dielectric constant of the nano-porous silicon.
(FR) L'invention concerne un substrat de réseau actif et son procédé de fabrication, le procédé de fabrication consistant à : fournir un substrat (10); former une électrode de grille sur le substrat (10); former de manière séquentielle une couche d'isolation d'électrode de grille (22), une couche semiconductrice et une couche de contact ohmique (24) sur un substrat transparent et l'électrode de grille; former une électrode de source (25) et une électrode de drain (26) sur la couche de contact ohmique (24); former une couche de protection (30) sur l'électrode de source (25) et l'électrode de drain (26); former une couche d'électrode de pixel (50) sur la couche de protection (30), la couche d'électrode de pixel (50) étant électriquement connectée à l'électrode de drain (26); la couche d'isolation d'électrode de grille (22) comprenant du silicium nano-poreux et des nanoparticules, la constante diélectrique des nanoparticules étant supérieure à la constante diélectrique du silicium nano-poreux.
(ZH) 一种主动阵列基板及其制造方法,制造方法包括:提供基板(10);形成栅极于基板(10)上;依序形成栅极绝缘层(22)、半导体层及欧姆接触层(24)于透明基材及所述栅极上;形成源电极(25)及漏电极(26)于所述欧姆接触层(24)上;形成保护层(30)于所述源电极(25)及所述漏电极(26)上;以及形成像素电极层(50)于所述保护层(30)上,其中所述像素电极层(50)是电性连接于所述漏电极(26);其中,所述栅极绝缘层(22)包括纳米多孔硅及纳米颗粒,所述纳米颗粒的介电常数大于纳米多孔硅的介电常数。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)