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1. (WO2018120543) METHOD FOR MANUFACTURING PIXEL STRUCTURE
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Pub. No.: WO/2018/120543 International Application No.: PCT/CN2017/082109
Publication Date: 05.07.2018 International Filing Date: 27.04.2017
IPC:
G02F 1/133 (2006.01)
G PHYSICS
02
OPTICS
F
DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1
Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01
for the control of the intensity, phase, polarisation or colour
13
based on liquid crystals, e.g. single liquid crystal display cells
133
Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
Applicants:
惠科股份有限公司 HKC CORPORATION LIMITED [CN/CN]; 中国广东省深圳市 宝安区石岩街道水田村民营工业园惠科工业园 Huike Industrial Park, Minying Industrial Park, Shuitian Country, Shiyan, Baoan District Shenzhen, Guangdong 518000, CN
重庆惠科金渝光电科技有限公司 CHONGQING HKC OPTOELECTRONICS TECHNOLOGY CO., LTD. [CN/CN]; 中国重庆市 巴南区界石镇石桂大道16号3幢4-1 No.4-1 3 Building, No.16, Shigui Avenue, Jieshi Town, Banan District Chongqing 400000, CN
Inventors:
陈猷仁 CHEN, YU-JEN; CN
Agent:
深圳市百瑞专利商标事务所(普通合伙) SHENZHEN BAIRUI PATENT & TRADEMARK OFFICE; 中国广东省深圳市 福田竹子林益华综合楼A栋205 Room 205 Building A, Yihua Complex Building, Zhuzi Lin, Futian District Shenzhen, Guangdong 518000, CN
Priority Data:
201611270994.430.12.2016CN
Title (EN) METHOD FOR MANUFACTURING PIXEL STRUCTURE
(FR) PROCÉDÉ DE FABRICATION D'UNE STRUCTURE DE PIXEL
(ZH) 像素结构的制造方法
Abstract:
(EN) A method for manufacturing a pixel structure, comprising: forming a first conductive layer (11) on a substrate (101), forming a second conductive layer (12) on the substrate (101), forming a third conductive layer (13) on the substrate (101), wherein the first conductive layer (11), the second conductive layer (12) and the third conductive layer (13) are arranged in a stacked and spaced apart manner, the first conductive layer (11), the second conductive layer (12) and the third conductive layer (13) covering each other in vertical space; an active switch (TFT) is formed in a pixel area after the first conductive layer (11) is formed, wherein the first conductive layer (11) and a drain of the active switch (TFT) are coupled, while the second conductive layer (12) and a first voltage line are coupled, and the third conductive layer (13) and a second voltage line are coupled. The present invention may maintain pixel voltage size, reduce the impact of parasitic capacitance, thereby increasing the impact of the coupling effect.
(FR) La présente invention concerne un procédé de fabrication d'une structure de pixel, consistant : à former une première couche conductrice (11) sur un substrat (101), à former une deuxième couche conductrice (12) sur le substrat (101), à former une troisième couche conductrice (13) sur le substrat (101), la première couche conductrice (11), la deuxième couche conductrice (12) et la troisième couche conductrice (13) étant agencées de manière empilée et espacée, la première couche conductrice (11), la deuxième couche conductrice (12) et la troisième couche conductrice (13) se recouvrant l'une l'autre dans l'espace vertical ; un commutateur actif (TFT) est formé dans une zone de pixel après la formation de la première couche conductrice (11), la première couche conductrice (11) et un drain du commutateur actif (TFT) étant couplés, tandis que la seconde couche conductrice (12) et une première ligne de tension sont couplées, et la troisième couche conductrice (13) et une seconde ligne de tension sont couplées. La présente invention peut maintenir une taille de tension de pixel, réduire l'impact d'une capacité parasite, ce qui permet d'augmenter l'impact de l'effet de couplage.
(ZH) 一种像素结构的制造方法,包括:形成第一导电层(11)于基板(101)上;形成第二导电层(12)于基板(101)上;形成第三导电层(13)于基板(101)上,其中第一导电层(11)、第二导电层(12)和第三导电层(13)三者叠放且间隔设置,第一导电层(11)、第二导电层(12)和第三导电层(13)三者在垂直空间上相互覆盖;以及在形成第一导电层(11)后,形成主动开关(TFT)于像素区内,其中第一导电层(11)和主动开关(TFT)的漏极耦合;第二导电层(12)和第一电压线耦合;第三导电层(13)和第二电压线耦合。保持像素电压大小,减小寄生电容的影响,从而改善耦合效应的影响。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)