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1. (WO2018111268) MICROELECTRONIC DEVICES DESIGNED WITH MOLD PATTERNING TO CREATE PACKAGE-LEVEL COMPONENTS FOR HIGH FREQUENCY COMMUNICATION SYSTEMS
Latest bibliographic data on file with the International Bureau   

Pub. No.: WO/2018/111268 International Application No.: PCT/US2016/066717
Publication Date: 21.06.2018 International Filing Date: 14.12.2016
IPC:
H01L 23/66 (2006.01) ,H01L 23/522 (2006.01) ,H01L 25/04 (2006.01) ,H01L 23/538 (2006.01) ,H01L 23/00 (2006.01) ,H01Q 1/22 (2006.01) ,H01Q 9/04 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
58
Structural electrical arrangements for semiconductor devices not otherwise provided for
64
Impedance arrangements
66
High-frequency adaptations
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
522
including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
538
the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
Q
AERIALS
1
Details of, or arrangements associated with, aerials
12
Supports; Mounting means
22
by structural association with other equipment or articles
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
Q
AERIALS
9
Electrically-short aerials having dimensions not more than twice the operating wavelength and consisting of conductive active radiating elements
04
Resonant aerials
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
EID, Feras; US
OSTER, Sasha N.; US
KAMGAING, Telesphor; US
DOGIAMIS, Georgios C.; US
ALEKSOV, Aleksandar; US
Agent:
BRASK, Justin, K.; US
Priority Data:
Title (EN) MICROELECTRONIC DEVICES DESIGNED WITH MOLD PATTERNING TO CREATE PACKAGE-LEVEL COMPONENTS FOR HIGH FREQUENCY COMMUNICATION SYSTEMS
(FR) DISPOSITIFS MICROÉLECTRONIQUES CONÇUS AVEC UNE FORMATION DE MOTIFS DE MOULE POUR CRÉER DES COMPOSANTS AU NIVEAU DU BOÎTIER POUR DES SYSTÈMES DE COMMUNICATION HAUTE FRÉQUENCE
Abstract:
(EN) Embodiments of the invention include a microelectronic device that includes a first substrate having radio frequency (RF) components and a second substrate that is coupled to the first substrate. The second substrate includes a first conductive layer of an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher. A mold material is disposed on the first and second substrates. The mold material includes a first region that is positioned between the first conductive layer and a second conductive layer of the antenna unit with the mold material being a dielectric material to capacitively couple the first and second conductive layers of the antenna unit.
(FR) Des modes de réalisation de l'invention concernent un dispositif microélectronique qui comprend un premier substrat ayant des composants radiofréquence (RF) et un second substrat qui est couplé au premier substrat. Le second substrat comprend une première couche conductrice d'une unité antenne pour émettre et recevoir des communications à une fréquence d'environ 4 GHz ou plus. Un matériau de moule est disposé sur les premier et second substrats. Le matériau de moule comprend une première région qui est positionnée entre la première couche conductrice et une seconde couche conductrice de l'unité d'antenne, le matériau de moule étant un matériau diélectrique pour coupler de manière capacitive les première et seconde couches conductrices de l'unité d'antenne.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)