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1. (WO2018108005) METHOD FOR REDUCING IMPACT OF BASAL PLANE DISLOCATION ON SILICON CARBIDE EPITAXIAL LAYER

Pub. No.:    WO/2018/108005    International Application No.:    PCT/CN2017/114685
Publication Date: Fri Jun 22 01:59:59 CEST 2018 International Filing Date: Thu Dec 07 00:59:59 CET 2017
IPC: H01L 21/28
Applicants: CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION NO.55 RESEARCH INSTITUTE
中国电子科技集团公司第五十五研究所
Inventors: LI, Yun
李赟
Title: METHOD FOR REDUCING IMPACT OF BASAL PLANE DISLOCATION ON SILICON CARBIDE EPITAXIAL LAYER
Abstract:
A method for reducing the impact of basal plane dislocation on a silicon carbide epitaxial layer, comprising using interface high-temperature annealing processing on a silicon carbide substrate to facilitate the downward movement of a BPD-TED conversion point away from the surface of a high-doped buffer layer, reducing the concentration difference between the high-doped buffer layer and an epitaxial layer by means of adding a graded buffer layer, and repairing the high-temperature hydrogen-etched high-doped buffer layer interface using a low-speed epitaxial mode, the reinforcing characteristics of the lateral epitaxial growth repairing surface corrosion pits of the high-doped buffer layer, thereby improving the surface quality of the subsequent epitaxial layer. The present method can lower the basal plane dislocation point to below the high-doped buffer layer interface, effectively reducing the likelihood of derived layer dislocation defects in the epitaxial layer due to basal plane dislocation under the action of a large current; and the process is compatible with common epitaxial processes.