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1. (WO2018106866) WRITE ASSIST FOR MEMORIES WITH RESISTIVE BIT LINES

Pub. No.:    WO/2018/106866    International Application No.:    PCT/US2017/065021
Publication Date: Fri Jun 15 01:59:59 CEST 2018 International Filing Date: Fri Dec 08 00:59:59 CET 2017
IPC: G11C 11/419
G11C 11/412
Applicants: AMPERE COMPUTING LLC
Inventors: HOMER, Russell
CHANDRASHEKAR, Abhiram Saligram
YEUNG, Alfred
Title: WRITE ASSIST FOR MEMORIES WITH RESISTIVE BIT LINES
Abstract:
Techniques efficiently assist in performing write operations in memories with resistive bit lines. A memory can comprise memory cells associated with respective word lines and bit lines. A write assist component can be associated with a subset of the memory cells associated with a bit line. Configuration of the write assist component can be based on the type of transistors employed by write circuits associated with the memory cells. During a write operation, the write assist component adds an additional current path to the ground, or the power supply, or both, at or in proximity to the far end of the write bit line when an appropriate write polarity is applied to the bit line by the driver at the other end of the bit line. This mitigates the effects of resistance of the bit line, which mitigates IR loss of the write signal.