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1. (WO2018106450) RESISTIVE RANDOM ACCESS MEMORY CELL
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Pub. No.: WO/2018/106450 International Application No.: PCT/US2017/062878
Publication Date: 14.06.2018 International Filing Date: 21.11.2017
IPC:
H01L 27/24 (2006.01) ,G11C 13/00 (2006.01) ,H01L 45/00 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
24
including solid state components for rectifying, amplifying, or switching without a potential-jump barrier or surface barrier
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
13
Digital stores characterised by the use of storage elements not covered by groups G11C11/, G11C23/, or G11C25/173
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
45
Solid state devices specially adapted for rectifying, amplifying, oscillating, or switching without a potential-jump barrier or surface barrier, e.g. dielectric triodes; Ovshinsky-effect devices; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
Applicants:
MICROSEMI SOC CORP. [US/US]; 3870 North First Street San Jose, California 95134, US
Inventors:
MCCOLLUM, John, L.; US
Agent:
D'ALESSANDRO, Kenneth, A.; US
GLASS, Kenneth; US
KAHN, Simon; IL
Priority Data:
62/432,04709.12.2016US
Title (EN) RESISTIVE RANDOM ACCESS MEMORY CELL
(FR) CELLULE DE MÉMOIRE VIVE RÉSISTIVE
Abstract:
(EN) A resistive random access memory cell includes three resistive random access memory devices (102, 104, 106), each resistive random access memory device having an ion source layer (156, 166, 186) and a solid electrolyte layer (154, 164, 188). The first and second resistive random access memory devices are connected in series such that either both ion source layers or both solid electrolyte layers are adjacent to one another. The third resistive random access memory device is connected in series with the first and second resistive random access memory devices.
(FR) L'invention concerne une cellule de mémoire vive résistive comprenant trois dispositifs de mémoire vive résistive (102, 104, 106), chaque dispositif de mémoire vive résistive ayant une couche de source d'ions (156, 166, 186) et une couche d'électrolyte solide (154, 164, 188). Les premier et second dispositifs de mémoire vive résistive sont connectés en série de telle sorte que soit les deux couches de source d'ions soit les deux couches d'électrolyte solide sont adjacentes les unes aux autres. Le troisième dispositif de mémoire vive résistive est connecté en série avec les premier et second dispositifs de mémoire vive résistive.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)