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1. (WO2018106315) ASYMMETRIC GATED FIN FIELD EFFECT TRANSISTOR (FET) (FINFET) DIODES
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Pub. No.: WO/2018/106315 International Application No.: PCT/US2017/053373
Publication Date: 14.06.2018 International Filing Date: 26.09.2017
Chapter 2 Demand Filed: 20.03.2018
IPC:
H01L 29/739 (2006.01) ,H01L 29/08 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
70
Bipolar devices
72
Transistor-type devices, i.e. able to continuously respond to applied control signals
739
controlled by field effect
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
06
characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
08
with semiconductor regions connected to an electrode carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
Applicants:
QUALCOMM INCORPORATED [US/US]; Attn: International IP Administration 5775 Morehouse Drive San Diego, California 92121-1714, US
Inventors:
WANG, Hao; US
YANG, Haining; US
CHEN, Xiaonan; US
Agent:
TERRANOVA, Steven N.; US
Priority Data:
15/371,51207.12.2016US
Title (EN) ASYMMETRIC GATED FIN FIELD EFFECT TRANSISTOR (FET) (FINFET) DIODES
(FR) DIODES DE TRANSISTOR À EFFET DE CHAMP À AILETTE (FINFET) À GRILLE ASYMÉTRIQUE
Abstract:
(EN) Asymmetric gated fin field effect transistor (FET) (finFET) diodes are disclosed. In one aspect, an asymmetric gated finFET diode employs a substrate that includes a well region of a first-type and a fin disposed in a direction. A first source/drain region is employed that includes a first-type doped material disposed in the fin having a first length in the direction. A second source/drain region having a second length in the direction larger than the first length is employed that includes a second-type doped material disposed in the fin. A gate region is disposed between the first source/drain region and the second source/drain region and has a third length in the direction that is larger than the first length and larger than the second length. The wider gate region increases a length of a depletion region of the asymmetric gated finFET diode, which reduces current leakage while avoiding increase in area.
(FR) L'invention concerne des diodes de transistor à effet de champ (FET) à ailette (finFET) à grille asymétrique. Selon un aspect, une diode finFET à grille asymétrique utilise un substrat qui comprend une région de puits d'un premier type et une ailette disposée dans une direction. Une première région de source/drain est utilisée et comprend un matériau dopé de premier type disposé dans l'ailette ayant une première longueur dans la direction. Une seconde région de source/drain ayant une deuxième longueur dans la direction supérieure à la première longueur est utilisée et comprend un matériau dopé de second type disposé dans l'ailette. Une région de grille est disposée entre la première région de source/drain et la seconde région de source/drain et a une troisième longueur dans la direction qui est supérieure à la première longueur et supérieure à la deuxième longueur. La région de grille plus large augmente la longueur d'une région d'appauvrissement de la diode finFET à grille asymétrique, ce qui réduit la fuite de courant tout en évitant une augmentation de la surface.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)