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1. (WO2018105486) SEMICONDUCTOR DEVICE
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Pub. No.: WO/2018/105486 International Application No.: PCT/JP2017/043053
Publication Date: 14.06.2018 International Filing Date: 30.11.2017
IPC:
H01L 25/07 (2006.01) ,H01L 23/29 (2006.01) ,H01L 25/18 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
07
the devices being of a type provided for in group H01L29/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
28
Encapsulation, e.g. encapsulating layers, coatings
29
characterised by the material
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
18
the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/-H01L51/160
Applicants:
株式会社 東芝 KABUSHIKI KAISHA TOSHIBA [JP/JP]; 東京都港区芝浦一丁目1番1号 1-1, Shibaura 1-chome, Minato-ku, Tokyo 1058001, JP
Inventors:
瀧本 和靖 TAKIMOTO, Kazuyasu; JP
市倉 優太 ICHIKURA, Yuta; JP
大部 利春 OHBU, Toshiharu; JP
伊東 弘晃 ITO, Hiroaki; JP
渡邉 尚威 WATANABE, Naotake; JP
田多 伸光 TADA, Nobumitsu; JP
山成 真輝 YAMANARI, Naoki; JP
平塚 大祐 HIRATSUKA, Daisuke; JP
関谷 洋紀 SEKIYA, Hiroki; JP
久里 裕二 HISAZATO, Yuuji; JP
飯尾 尚隆 IIO, Naotaka; JP
松村 仁嗣 MATSUMURA, Hitoshi; JP
Agent:
日向寺 雅彦 HYUGAJI, Masahiko; JP
Priority Data:
2016-23640806.12.2016JP
Title (EN) SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEURS
(JA) 半導体装置
Abstract:
(EN) According to one embodiment of the present invention, a semiconductor device is provided with a first metal plate, a second metal plate and two or more semiconductor units. The two or more semiconductor units are arranged on the first metal plate. Each one of the two or more semiconductor units comprises a first metal member, a second metal member and a semiconductor element. The first metal member comprises a first connection surface that is connected to the first main surface. The second metal member comprises a second connection surface that is connected to the second main surface. The semiconductor element comprises an active region which has surfaces that respectively face the first connection surface and the second connection surface. The area of the first connection surface is larger than the area of the surface of the active region facing the first connection surface. The area of the second connection surface is larger than the area of the surface of the active region facing the second connection surface.
(FR) Selon un mode de réalisation de la présente invention, un dispositif à semi-conducteurs est pourvu de première et seconde plaques métalliques, et d'au moins deux unités semi-conductrices. Lesdites unités semi-conductrices sont disposées sur la première plaque métallique. Chacune desdites unités semi-conductrices est pourvue de premier et second éléments métalliques et d'un élément semi-conducteur. Le premier élément métallique comprend une première surface de liaison liée à la première surface principale. Le second élément métallique comprend une seconde surface de liaison liée à la seconde surface principale. L'élément semi-conducteur comprend une région active présentant des surfaces qui font respectivement face à la première et à la seconde surface de liaison. L'aire de la première surface de liaison est plus grande que l'aire de la surface de la région active faisant face à la première surface de liaison. L'aire de la seconde surface de liaison est plus grande que l'aire de la surface de la région active faisant face à la seconde surface de liaison.
(JA) 実施形態によれば、半導体装置は、第1金属板と、第2金属板と、2以上の半導体ユニットと、を備える。前記2以上の半導体ユニットは、前記第1金属板上に配置されている。前記2以上の半導体ユニットのそれぞれは、第1金属部材と、第2金属部材と、半導体素子と、を含む。前記第1金属部材は、前記第1主面に接続される第1接続面を含む。前記第2金属部材は、前記第2主面に接続される第2接続面を含む。前記半導体素子は、前記第1接続面および前記第2接続面にそれぞれ対向する面を有するアクティブ領域を含む。前記第1接続面の面積は、前記第1接続面に対向する前記アクティブ領域の面の面積よりも大きい。前記第2接続面の面積は、前記第2接続面に対向する前記アクティブ領域の面の面積よりも大きい。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)