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Pub. No.: WO/2018/105326 International Application No.: PCT/JP2017/040815
Publication Date: 14.06.2018 International Filing Date: 13.11.2017
IPC:
H01L 33/62 (2010.01) ,H01L 23/02 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
48
characterised by the semiconductor body packages
62
Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
02
Containers; Seals
Applicants: NIKKISO CO., LTD.[JP/JP]; 20-3, Ebisu 4-chome, Shibuya-ku Tokyo 1506022, JP
Inventors: NIIZEKI Shoichi; JP
ICHINOKURA Hiroyasu; JP
Agent: MORISHITA Sakaki; JP
Priority Data:
2016-23760707.12.2016JP
Title (EN) OPTICAL SEMICONDUCTOR DEVICE
(FR) DISPOSITIF OPTIQUE À SEMICONDUCTEUR
(JA) 光半導体装置
Abstract:
(EN) An optical semiconductor device 10 comprising: an optical semiconductor element 12 having a light-transmitting support substrate 20, a buffer layer 22 upon the support substrate 20, a seal ring (e.g., a first electrode 32) provided in a frame shape upon an outer peripheral area 60 of the buffer layer 22, an active layer 26 provided upon an inner area 62 of the buffer layer 22, and an electrode (e.g., a second electrode 34) provided upon the active layer 26; a mounting substrate 14 to which the optical semiconductor element 12 is attached; and a sealing section 16 that seals between the seal ring and the mounting substrate 14.
(FR) L'invention concerne un dispositif à semiconducteur optique 10 comprenant : un élément semiconducteur optique 12 ayant un substrat de support de transmission de lumière 20, une couche tampon 22 sur le substrat de support 20, un anneau d'étanchéité (par exemple, une première électrode 32) disposé dans une forme de cadre sur une zone périphérique externe 60 de la couche tampon 22, une couche active 26 disposée sur une zone interne 62 de la couche tampon 22, et une électrode (par exemple, une seconde électrode 34) disposée sur la couche active 26; un substrat de montage 14 auquel est fixé l'élément semiconducteur optique 12; et une section d'étanchéité 16 qui assure l'étanchéité entre l'anneau d'étanchéité et le substrat de montage 14.
(JA) 光半導体装置10は、透光性の支持基板20と、支持基板20上のバッファ層22と、バッファ層22の外周領域60上に枠状に設けられるシールリング(例えば第1電極32)と、バッファ層22の内側領域62上に設けられる活性層26と、活性層26上に設けられる電極(例えば第2電極34)とを有する光半導体素子12と、光半導体素子12が実装される実装基板14と、シールリングと実装基板14の間を封止する封止部16と、を備える。
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)