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1. (WO2018105219) SEMICONDUCTOR DEVICE AND METHOD FOR DESIGNING SEMICONDUCTOR DEVICE
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Pub. No.: WO/2018/105219 International Application No.: PCT/JP2017/036397
Publication Date: 14.06.2018 International Filing Date: 29.09.2017
IPC:
H01L 29/778 (2006.01) ,H01L 23/373 (2006.01) ,H01L 29/20 (2006.01) ,H01L 29/10 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
778
with two-dimensional charge carrier gas channel, e.g. HEMT
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
34
Arrangements for cooling, heating, ventilating or temperature compensation
36
Selection of materials, or shaping, to facilitate cooling or heating, e.g. heat sinks
373
Cooling facilitated by selection of materials for the device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
12
characterised by the materials of which they are formed
20
including, apart from doping materials or other impurities, only AIIIBV compounds
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
06
characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
10
with semiconductor regions connected to an electrode not carrying current to be rectified, amplified, or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
Applicants:
MITSUBISHI ELECTRIC CORPORATION [JP/JP]; 7-3, Marunouchi 2-chome, Chiyoda-ku, Tokyo 100-8310 Japan, JP
Inventors:
TEO, Koon Hoo; US
TANG, Chenjie; US
LIN, Chungwei; US
Agent:
SOGA, Michiharu; S. Soga & Co. 8th Floor, Kokusai Building 1-1, Marunouchi 3-chome Chiyoda-ku, Tokyo 100-0005, JP
Priority Data:
15/371,36007.12.2016US
Title (EN) SEMICONDUCTOR DEVICE AND METHOD FOR DESIGNING SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMICONDUCTEUR ET PROCÉDÉ DE CONCEPTION D'UN DISPOSITIF À SEMICONDUCTEUR
Abstract:
(EN) A semiconductor device includes a substrate (10), a back-barrier layer (11) arranged on the substrate, the back-barrier layer including first p-type dopant atoms, an intermediate or nucleation layer (12) having a lattice constant different from a lattice constant of the back-barrier layer, a semiconductor heterostructure having a channel layer (13), a spacer layer (14) on the channel layer and a barrier layer (15) on the spacer layer, wherein a combination of materials of the barrier layer, the spacer layer and the channel layer is selected such that a carrier charge is provided to the channel layer, a gate layer (18) arranged to partially cover a top of the barrier layer, wherein the gate layer includes second p-type dopant atoms, and a set of electrodes (S, G, D) for providing and controlling the carrier charge in the carrier channel.
(FR) L'invention concerne un dispositif à semiconducteur comprenant un substrat (10), une couche de barrière arrière (11) disposée sur le substrat, la couche de barrière arrière comprenant des premiers atomes de dopant de type p, une couche intermédiaire ou de nucléation (12) ayant une constante de réseau différente d'une constante de réseau de la couche de barrière arrière, une hétérostructure semiconductrice ayant une couche de canal (13), une couche d'espacement (14) sur la couche de canal et une couche barrière (15) sur la couche d'espacement, une combinaison de matériaux de la couche barrière, de la couche d'espacement et de la couche de canal étant sélectionnée de telle sorte qu'une charge porteuse est fournie à la couche de canal, une couche de grille (18) agencée pour recouvrir partiellement une partie supérieure de la couche barrière, la couche de grille comprenant des seconds atomes de dopant de type p, et un ensemble d'électrodes (S, G, D) pour fournir et commander la charge porteuse dans le canal porteur.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)