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1. (WO2018104711) MEMORY PROTECTION LOGIC

Pub. No.:    WO/2018/104711    International Application No.:    PCT/GB2017/053644
Publication Date: Fri Jun 15 01:59:59 CEST 2018 International Filing Date: Tue Dec 05 00:59:59 CET 2017
IPC: G06F 12/14
G06F 9/44
G06F 21/74
Applicants: NORDIC SEMICONDUCTOR ASA
WILSON, Timothy James
Inventors: AUNE, Frank
Title: MEMORY PROTECTION LOGIC
Abstract:
A resettable microcontroller (1) comprising a processor (7), a memory (11, 13), a memory bus, and memory protection logic (9). The microcontroller (1) is arranged to clear a set of memory- protection configuration registers (26) whenever the microcontroller (1) is reset. The memory protection logic (9) is arranged to access the set of memory-protection configuration registers (26) and is configured to monitor memory access requests on the bus; detect when a memory access request attempts to access a memory address in a protectable region of the memory (11, 13); determine whether the memory access request satisfies an access criterion for the protectable region, the access criterion depending on data stored in the set of memory- protection configuration registers (26); block the memory access request when the access criterion is not satisfied; and prevent writing to any memory-protection configuration register (26) unless the memory-protection configuration register (26) is in a cleared state.