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1. (WO2018103275) SOC CHIP HAVING DEBUGGING INTERFACE SECURITY MECHANISM, AND METHOD

Pub. No.:    WO/2018/103275    International Application No.:    PCT/CN2017/085624
Publication Date: Fri Jun 15 01:59:59 CEST 2018 International Filing Date: Thu May 25 01:59:59 CEST 2017
IPC: G06F 21/60
Applicants: SHANGHAI INDUSTRIAL μTECHNOLOGY RESEARCH INSTITUTE
上海新微技术研发中心有限公司
Inventors: WANG, Jian
王健
YANG, Canhua
杨灿华
Title: SOC CHIP HAVING DEBUGGING INTERFACE SECURITY MECHANISM, AND METHOD
Abstract:
Provided are a SOC chip having a debugging interface security mechanism, and a method. The chip comprises: a debugging port; a microprocessor, comprising a debugging interface; a storage unit used for pre-storing a security access password of the debugging interface; and a security control unit connected between the debugging port and the debugging interface, and used for monitoring an input timing of an external device connected to the debugging port. When the input timing is correct, an input password is compared with the security access password of the debugging interface; if the comparison result is consistent, a channel from the debugging port to the debugging interface is opened; and if the comparison result is inconsistent, the channel is closed. The present invention adds a security control unit between a physical debugging port and an internal debugging interface, so as to isolate same in terms of physical connection, and the debugging port and the internal debugging interface can be physically connected only when a timing waveform signal including a correct password is input on the debugging port, thereby acquiring a right to access an internal resource.