Search International and National Patent Collections

1. (WO2018103274) SOC CHIP HAVING TAMPER-RESISTANT MECHANISM FOR INTERNAL DATA OF MEMORY, AND METHOD THEREFOR

Pub. No.:    WO/2018/103274    International Application No.:    PCT/CN2017/085623
Publication Date: Fri Jun 15 01:59:59 CEST 2018 International Filing Date: Thu May 25 01:59:59 CEST 2017
IPC: G06F 12/14
Applicants: SHANGHAI INDUSTRIAL μTECHNOLOGY RESEARCH INSTITUTE
上海新微技术研发中心有限公司
Inventors: WANG, Jian
王健
YANG, Canhua
杨灿华
Title: SOC CHIP HAVING TAMPER-RESISTANT MECHANISM FOR INTERNAL DATA OF MEMORY, AND METHOD THEREFOR
Abstract:
Provided are an SOC chip having a tamper-resistant mechanism for internal data of a memory, and a method, the chip comprising: a first storage unit for storing sensitive system data, the maintenance thereof being the responsibility of a chip production provider; a second storage unit for storing user data and a program, the maintenance thereof being the responsibility of a user; a microprocessor for accessing the first storage unit and second storage unit; an access control unit which is connected between the microprocessor and the first storage unit and between the microprocessor and the second storage unit, and which is used for completing control over a time sequence of the microprocessor accessing the first storage unit and second storage unit; and a characteristic value unit, which is connected to the microprocessor, and is used for calculating a characteristic value of a user code in the second storage unit, and comparing same to a feature value pre-stored in the first storage unit so as to determine whether the user code has been illegally tampered with. The invention, by means of a characteristic value verification circuit which has been powered on, can detect whether an NVM memory has accidentally lost data, improving the reliability of a chip.