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1. (WO2018103117) CHIP PACKAGING STRUCTURE, AND PACKAGING METHOD THEREOF
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Pub. No.: WO/2018/103117 International Application No.: PCT/CN2016/109499
Publication Date: 14.06.2018 International Filing Date: 12.12.2016
IPC:
H01L 23/31 (2006.01) ,H01L 23/488 (2006.01) ,H01L 21/48 (2006.01) ,H01L 21/56 (2006.01) ,H01L 21/683 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
28
Encapsulation, e.g. encapsulating layers, coatings
31
characterised by the arrangement
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
48
Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads or terminal arrangements
488
consisting of soldered or bonded constructions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
48
Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/06-H01L21/326201
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
56
Encapsulations, e.g. encapsulating layers, coatings
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
67
Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components
683
for supporting or gripping
Applicants:
江阴长电先进封装有限公司 JIANGYIN CHANGDIAN ADVANCED PACKAGING CO., LTD [CN/CN]; 中国江苏省江阴市 高新技术产业开发园区澄江东路99号 No.99 Chengjiang East Road, Hi-Tech Industrial Parks Jiangyin, Jiangsu 214429, CN
Inventors:
张黎 ZHANG, Li; CN
徐虹 XU, Hong; CN
陈栋 CHEN, Dong; CN
陈锦辉 CHEN, Jinhui; CN
赖志明 LAI, Zhiming; CN
陈启才 CHEN, Qicai; CN
Agent:
南京经纬专利商标代理有限公司 NANJING JINGWEI PATENT & TRADEMARK AGENCY CO., LTD; 中国江苏省南京市 鼓楼区中山路179号12楼B座 12th FL.-B No. 179 Zhongshan Road, Gulou Nanjing, Jiangsu 210005, CN
Priority Data:
201611107747.206.12.2016CN
Title (EN) CHIP PACKAGING STRUCTURE, AND PACKAGING METHOD THEREOF
(FR) STRUCTURE DE CONDITIONNEMENT DE PUCE, ET SON PROCÉDÉ DE CONDITIONNEMENT
(ZH) 一种芯片封装结构及其封装方法
Abstract:
(EN) The present invention relates to the technical field of semiconductor packaging, and provides a chip packaging structure, and packaging method thereof. The structure comprises a silicon-based main body (1) and chip electrodes (11). The silicon-based main body (1) is provided with a passivation layer (12) and passivation layer openings (121) on a front face thereof. The chip electrodes (11) have rear faces embedded in the front face of the silicon-based main body (1). The passivation layer openings (121) expose front faces of the chip electrodes (11). A dielectric layer (4) is provided on an upper surface of the passivation layer (12), and dielectric layer openings (41) are provided. Metal protrusion structures (5) are provided on the front faces of the chip electrodes (11). An encapsulation layer (3) is provided on side walls and a rear face of the silicon-based main body (1). The chip packaging structure of the present invention employs insulation protection on side walls to avoid electrical leakage and short circuit conditions, thus increasing reliability and improving the pass rate of chip mounting. By providing recesses on a rear face of a wafer to divide the wafer into individual chip units, and employing a protection technique in the surrounding and rear surfaces of the individual chip units, the packaging method of the present invention eliminates wafer reconfiguration, and effectively improves production efficiency for small-sized chips, thus reducing costs.
(FR) La présente invention se rapporte au champ technique du conditionnement de semi-conducteurs, et concerne une structure de conditionnement de puce, et son procédé de conditionnement. La structure comprend un corps principal (1) à base de silicium et des électrodes de puce (11). Le corps principal (1) à base de silicium comporte une couche de passivation (12) et des ouvertures (121) de couche de passivation sur sa face avant. Les électrodes de puce (11) ont des faces arrière incorporées dans la face avant du corps principal (1) à base de silicium. Les ouvertures (121) de couche de passivation découvrent les faces avant des électrodes de puce (11). Une couche diélectrique (4) est disposée sur une surface supérieure de la couche de passivation (12), et des ouvertures (41) de couche diélectrique sont réalisées. Des structures en saillie (5) de métal sont disposées sur les faces avant des électrodes de puce (11). Une couche d’encapsulation (3) est disposée sur des parois latérales et une face arrière du corps principal (1) à base de silicium. La structure de conditionnement de puce selon la présente invention emploie une protection d’isolation sur des parois latérales pour éviter des conditions de fuite électrique et de court-circuit, accroissant ainsi la fiabilité et améliorant ainsi le taux d’acceptation de montage de puces. En aménageant des évidements sur une face arrière d’une plaquette pour diviser la plaquette en unités de puces individuelles, et en employant une technique de protection dans les surfaces de contour et les surfaces arrière des unités de puces individuelles, le procédé de conditionnement selon la présente invention élimine la reconfiguration de plaquettes, et améliore efficacement le rendement de production pour des puces de petite taille, réduisant ainsi les coûts.
(ZH) 提供一种芯片封装结构及其封装方法,属于半导体封装技术领域。其包括硅基本体(1)和芯片电极(11),所述硅基本体(1)的正面设置钝化层(12)并开设钝化层开口(121),所述芯片电极(11)由背面嵌入于硅基本体(1)的正面,所述钝化层开口(121)露出芯片电极(11)的正面,所述钝化层(12)的上表面设置介电层(4)并开设介电层开口(41),所述芯片电极(11)的正面设置金属凸块结构(5);所述硅基本体(1)的侧壁和背面设置包封层(3)。上述芯片封装结构采用了侧壁绝缘保护,不易漏电或短路,提高可靠性以及改善芯片贴装良率。上述封装方法采用在晶圆背面设置沟槽,将晶圆分割成芯片单体,并实施芯片单体四周和背面保护技术,这种方法避免了晶圆重构,对于较小芯片来说,有效地提高了产能,进一步降低成本。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)