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1. (WO2018102596) DEFECT DISCOVERY AND RECIPE OPTIMIZATION FOR INSPECTION OF THREE-DIMENSIONAL SEMICONDUCTOR STRUCTURES
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Pub. No.: WO/2018/102596 International Application No.: PCT/US2017/064040
Publication Date: 07.06.2018 International Filing Date: 30.11.2017
IPC:
G01N 21/95 (2006.01) ,G01N 21/88 (2006.01) ,G01N 21/01 (2006.01)
G PHYSICS
01
MEASURING; TESTING
N
INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
21
Investigating or analysing materials by the use of optical means, i.e. using infra-red, visible, or ultra-violet light
84
Systems specially adapted for particular applications
88
Investigating the presence of flaws, defects or contamination
95
characterised by the material or shape of the object to be examined
G PHYSICS
01
MEASURING; TESTING
N
INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
21
Investigating or analysing materials by the use of optical means, i.e. using infra-red, visible, or ultra-violet light
84
Systems specially adapted for particular applications
88
Investigating the presence of flaws, defects or contamination
G PHYSICS
01
MEASURING; TESTING
N
INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
21
Investigating or analysing materials by the use of optical means, i.e. using infra-red, visible, or ultra-violet light
01
Arrangements or apparatus for facilitating the optical investigation
Applicants:
KLA-TENCOR CORPORATION [US/US]; Legal Dept. One Technology Drive Milpitas, California 95035, US
Inventors:
BHATTACHARYYA, Santosh; US
SHARMA, Devashish; US
MAHER, Christopher; US
HUA, Bo; CN
MEASOR, Philip; US
DANEN, Robert; US
Agent:
MCANDREWS, Kevin; US
MORRIS, Elizabeth M.N.; US
Priority Data:
15/826,01929.11.2017US
62/427,91730.11.2016US
62/427,97330.11.2016US
Title (EN) DEFECT DISCOVERY AND RECIPE OPTIMIZATION FOR INSPECTION OF THREE-DIMENSIONAL SEMICONDUCTOR STRUCTURES
(FR) DÉCOUVERTE DE DÉFAUTS ET OPTIMISATION DE RECETTE POUR L'INSPECTION DE STRUCTURES SEMI-CONDUCTRICES TRIDIMENSIONNELLES
Abstract:
(EN) Methods and systems for discovery of defects of interest (DOI) buried within three dimensional semiconductor structures and recipe optimization are described herein. The volume of a semiconductor wafer subject to defect discovery and verification is reduced by storing images associated with a subset of the total depth of the semiconductor structures under measurement. Image patches associated with defect locations at one or more focus planes or focus ranges are recorded. The number of optical modes under consideration is reduced based on any of a comparison of one or more measured wafer level defect signatures and one or more expected wafer level defect signatures, measured defect signal to noise ratio, and defects verified without de-processing. Furthermore, verified defects and recorded images are employed to train a nuisance filter and optimize the measurement recipe. The trained nuisance filter is applied to defect images to select the optimal optical mode for production.
(FR) L'invention concerne des procédés et des systèmes de découverte de défauts d'intérêt (DOI) enfouis dans des structures semi-conductrices tridimensionnelles et d'optimisation de recette. Le volume d'une tranche de semi-conducteur soumise à une découverte et une vérification de défauts est réduit par mémorisation d'images associées à un sous-ensemble de la profondeur totale des structures semi-conductrices faisant l'objet d'une mesure. Des parcelles d'image associées à des emplacements de défauts au niveau d'un ou de plusieurs plans de mise au point ou plages de mise au point sont enregistrées. Le nombre de modes optiques pris en considération est réduit sur la base d'un élément quelconque parmi une comparaison d'une ou de plusieurs signatures de défaut de niveau de tranche mesurées et d'une ou de plusieurs signatures de défaut de niveau de tranche prévues, un rapport signal/bruit de défaut mesuré, et des défauts vérifiés sans détraitement. En outre, des défauts vérifiés et des images enregistrées sont utilisés pour entraîner un filtre de nuisance et optimiser la recette de mesure. Le filtre de nuisance entraîné est appliqué à des images à défaut pour sélectionner le mode optique optimal pour la production.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)