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1. (WO2018102538) PROVIDING EXTENDED DYNAMIC RANDOM ACCESS MEMORY (DRAM) BURST LENGTHS IN PROCESSOR-BASED SYSTEMS

Pub. No.:    WO/2018/102538    International Application No.:    PCT/US2017/063921
Publication Date: Fri Jun 08 01:59:59 CEST 2018 International Filing Date: Fri Dec 01 00:59:59 CET 2017
IPC: G06F 13/16
G06F 13/28
Applicants: QUALCOMM INCORPORATED
Inventors: BAINS, Kuljit, Singh
QUEEN, Wesley
WANG, Liyong
Title: PROVIDING EXTENDED DYNAMIC RANDOM ACCESS MEMORY (DRAM) BURST LENGTHS IN PROCESSOR-BASED SYSTEMS
Abstract:
Providing extended dynamic random access memory (DRAM) burst lengths in processor-based systems is disclosed. In one aspect, a processor-based system includes a DRAM circuit (e.g., disposed on a common x4/x8 die) providing 4-bit-wide data access ("x4") and a 128-bit internal data prefetch. When operated in a x4 mode, the DRAM circuit is configured to provide an extended DRAM burst length of 32 bits ("BL32"). The DRAM circuit receives a memory read request from a memory controller communicatively coupled to the DRAM circuit, prefetches 128 bits of data, and returns all of the 128 bits of fetched data to the memory controller in response to the memory read request. In some aspects, the DRAM circuit may also receive a memory write command including 128 bits of write data from the memory controller, and write the 128 bits of write data to memory without performing a read/modify/write (RMW) operation.