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1. (WO2018102117) METHOD, APPARATUS AND SYSTEM FOR DYNAMIC CLOCK FREQUENCY CONTROL ON A BUS
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Pub. No.: WO/2018/102117 International Application No.: PCT/US2017/061463
Publication Date: 07.06.2018 International Filing Date: 14.11.2017
IPC:
G06F 1/08 (2006.01) ,G06F 13/38 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
1
Details not covered by groups G06F3/-G06F13/82
04
Generating or distributing clock signals or signals derived directly therefrom
08
Clock generators with changeable or programmable clock frequency
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
13
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38
Information transfer, e.g. on bus
Applicants:
INTEL CORPORATION [US/US]; 2200 Mission College Boulevard Santa Clara, California 95054, US
Inventors:
QUIET, Duane G.; US
SRIVASTAVA, Amit Kumar; US
FOUST, Kenneth P.; US
Agent:
ROZMAN, Mark J.; US
RICHARDS, Edwin E.; US
TROP, Timothy N.; US
GARZA, John C.; US
PRUNER JR., Fred G.; US
RIFAI, D'Ann Naylor; US
Priority Data:
15/366,00101.12.2016US
Title (EN) METHOD, APPARATUS AND SYSTEM FOR DYNAMIC CLOCK FREQUENCY CONTROL ON A BUS
(FR) PROCÉDÉ, APPAREIL ET SYSTÈME DE COMMANDE DYNAMIQUE DE FRÉQUENCE D'HORLOGE SUR UN BUS
Abstract:
(EN) In one embodiment, an apparatus includes a clock control circuit to generate a clock signal for communication on an interconnect. The clock control circuit may be configured to receive an indication of a next device of a plurality of devices to be accessed and to dynamically update a control signal to cause the communication of the clock signal to be dynamically switched between a fixed clock frequency and a spread spectrum clock frequency based at least in part on the indication of communication to the next device. Other embodiments are described and claimed.
(FR) Dans un mode de réalisation, un appareil comprend un circuit de commande d'horloge conçu pour générer un signal d'horloge en vue d'une communication sur une interconnexion. Le circuit de commande d'horloge peut être conçu pour recevoir une indication d'un prochain dispositif devant faire l'objet d'un accès, parmi une pluralité de dispositifs, et pour mettre à jour dynamiquement un signal de commande de façon à provoquer une commutation dynamique de la communication du signal d'horloge entre une fréquence d'horloge fixe et une fréquence d'horloge à étalement du spectre au moins en partie sur la base de l'indication de communication au prochain dispositif. L'invention concerne également d'autres modes de réalisation.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)