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1. (WO2018101770) TWO-TERMINAL VERTICAL TYPE 1T-DRAM AND MANUFACTURING METHOD THEREFOR

Pub. No.:    WO/2018/101770    International Application No.:    PCT/KR2017/013926
Publication Date: Fri Jun 08 01:59:59 CEST 2018 International Filing Date: Fri Dec 01 00:59:59 CET 2017
IPC: H01L 27/108
H01L 29/78
H01L 27/102
H01L 27/24
Applicants: INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY
한양대학교 산학협력단
Inventors: PARK, Jae Gun
박재근
SONG, Seung Hyun
송승현
KIM, Min Won
김민원
Title: TWO-TERMINAL VERTICAL TYPE 1T-DRAM AND MANUFACTURING METHOD THEREFOR
Abstract:
A two-terminal vertical type 1T-DRAM and a manufacturing method therefor are disclosed. According to one embodiment of the present invention, the two-terminal vertical type 1T-DRAM comprises: a cathode layer formed as a first-type high-concentration semiconductor layer; a base region including a second-type low-concentration semiconductor layer formed on the cathode layer and a first-type low-concentration semiconductor layer formed on the second-type low-concentration semiconductor layer; and an anode layer formed as a second-type high-concentration semiconductor layer on the first-type low-concentration semiconductor layer.