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1. (WO2018101468) ELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING ELECTRONIC COMPONENT
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Pub. No.: WO/2018/101468 International Application No.: PCT/JP2017/043339
Publication Date: 07.06.2018 International Filing Date: 01.12.2017
IPC:
H05K 1/16 (2006.01) ,H01G 4/12 (2006.01) ,H01G 4/33 (2006.01) ,H01L 23/12 (2006.01) ,H05K 3/46 (2006.01)
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1
Printed circuits
16
incorporating printed electric components, e.g. printed resistor, capacitor, inductor
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
G
CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
4
Fixed capacitors; Processes of their manufacture
002
Details
018
Dielectrics
06
Solid dielectrics
08
Inorganic dielectrics
12
Ceramic dielectrics
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
G
CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
4
Fixed capacitors; Processes of their manufacture
33
Thin- or thick-film capacitors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
46
Manufacturing multi-layer circuits
Applicants:
凸版印刷株式会社 TOPPAN PRINTING CO., LTD. [JP/JP]; 東京都台東区台東一丁目5番1号 5-1, Taito 1-chome, Taito-ku, Tokyo 1100016, JP
Inventors:
▲高▼城 総夫 TAKAGI, Fusao; JP
中村 清智 NAKAMURA, Kiyotomo; JP
Agent:
蔵田 昌俊 KURATA, Masatoshi; JP
野河 信久 NOGAWA, Nobuhisa; JP
河野 直樹 KOHNO, Naoki; JP
井上 正 INOUE, Tadashi; JP
Priority Data:
2016-23527702.12.2016JP
Title (EN) ELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING ELECTRONIC COMPONENT
(FR) COMPOSANT ÉLECTRONIQUE ET PROCÉDÉ DE FABRICATION DE COMPOSANT ÉLECTRONIQUE
(JA) 電子部品及び電子部品製造方法
Abstract:
(EN) An electronic component according to the present invention is provided with: a glass base material 100 having a through-hole 101 formed so as to pass through both surfaces thereof; an insulating resin layer 120 that is stacked on each of both surfaces of the glass base material 100 and that has a copper-plated layer 103 formed in the interior thereof; and a capacitor 109 having a lower electrode 110 formed on the copper-plated layer 103, a dielectric layer 111 formed so as to be stacked on the lower electrode 110, and an upper electrode 112 formed so as to be stacked on the dielectric layer 111. A region of the upper electrode 112, said region being along the surface of the copper-plated layer 103, is formed so as to be smaller than a region of the dielectric layer 111, said region being along the surface of the copper-plated layer 103, and a region of the lower electrode 110, said region being along the surface of the copper-plated layer 103. This provides a glass core substrate having a thin-film capacitor with a highly reliable MIM structure and also achieves a compact size, a small thickness, and high reliability.
(FR) La présente invention concerne un composant électronique qui comporte : un matériau de base (100) en verre ayant un trou traversant (101) formé de manière à traverser ses deux surfaces ; une couche de résine isolante (120) qui est empilée sur chacune de deux surfaces du matériau de base (100) en verre et à l’intérieur de laquelle est formée une couche à placage de cuivre (103) ; et un condensateur (109) ayant une électrode inférieure (110) formée sur la couche à placage de cuivre (103), une couche diélectrique (111) formée de manière à être empilée sur l’électrode inférieure (110), et une électrode supérieure (112) formée de manière à être empilée sur la couche diélectrique (111). Une zone de l’électrode supérieure (112), ladite zone étant le long de la surface de la couche à placage de cuivre (103), est formée de manière à être plus petite qu’une zone de la couche diélectrique (111), ladite zone étant le long de la surface de la couche à placage de cuivre (103), et une zone de l’électrode inférieure (110), ladite zone étant le long de la surface de la couche à placage de cuivre (103). Cela permet de réaliser un substrat à noyau de verre ayant un condensateur à couche mince avec une structure MIM à haute fiabilité et d’obtenir une taille compacte, une petite épaisseur, et une haute fiabilité.
(JA) 電子部品は、両面を貫通する貫通孔101が形成されたガラス基材100と、ガラス基材100の両面に積層され、内部に銅めっき層103が形成された絶縁樹脂層120と、銅めっき層103上に形成された下部電極110と、下部電極110上に積層形成される誘電体層111と、誘電体層111上に積層形成される上部電極112とを有するキャパシタ109とを備え、上部電極112における銅めっき層103の面に沿った領域は、誘電体層111の銅めっき層103の面に沿った領域及び下部電極110の銅めっき層103の面に沿った領域よりも小さく形成されることで、信頼性の高いMIM構造の薄膜キャパシタを有するガラスコア基板を有すると共に、小型化・薄型化・高信頼化を実現できる。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)