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1. (WO2018101404) METHOD FOR PROCESSING WIRING BOARD
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Pub. No.: WO/2018/101404 International Application No.: PCT/JP2017/043062
Publication Date: 07.06.2018 International Filing Date: 30.11.2017
IPC:
H05K 3/26 (2006.01) ,H05K 3/00 (2006.01) ,H05K 3/46 (2006.01)
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
22
Secondary treatment of printed circuits
26
Cleaning or polishing of the conductive pattern
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
46
Manufacturing multi-layer circuits
Applicants:
株式会社アルバック ULVAC, INC. [JP/JP]; 神奈川県茅ケ崎市萩園2500 2500, Hagisono, Chigasaki-shi, Kanagawa 2538543, JP
Inventors:
佐藤 宗之 SATO Muneyuki; JP
森川 泰宏 MORIKAWA Yasuhiro; JP
鈴木 実 SUZUKI Minoru; JP
Agent:
及川 周 OIKAWA Shu; JP
勝俣 智夫 KATSUMATA Tomoo; JP
土屋 亮 TSUCHIYA Ryo; JP
Priority Data:
2016-23505402.12.2016JP
Title (EN) METHOD FOR PROCESSING WIRING BOARD
(FR) PROCÉDÉ DE TRAITEMENT D'UN TABLEAU DE CONNEXIONS
(JA) 配線基板の加工方法
Abstract:
(EN) This method for processing a wiring board is a method for processing a wiring board including a configuration in which a conductor part locally disposed on the board is coated with a resin part formed by dispersing, in an organic member, an inorganic member constituting a filler, wherein the organic member is removed from a surface layer side of the resin part by using an ashing method, and the inorganic member remaining on the surface layer side of the resin part, from which the organic member has been removed, is removed by using a wet cleaning method.
(FR) La présente invention concerne un procédé de traitement d'un tableau de connexions qui comprend une configuration dans laquelle une partie conductrice disposée localement sur le tableau est revêtue d'une partie en résine formée par dispersion, dans un élément organique, d'un élément inorganique constituant une charge, l'élément organique étant éliminé d'un côté de la couche de surface de la partie en résine à l'aide d'un procédé de calcination, et l'élément inorganique, restant sur le côté de la couche de surface de la partie en résine d'où l'élément organique a été éliminé, étant éliminé à l'aide d'un procédé de nettoyage par voie humide.
(JA) 本発明の配線基板の加工方法は、基板上に局所的に配された導体部が、フィラーをなす無機部材が有機部材に分散してなる樹脂部によって被覆された構成を含む配線基板の加工方法であって、アッシング法を用い、前記樹脂部の表層側から前記有機部材を除去し、ウェット洗浄法を用い、前記有機部材が除去された樹脂部の表層側に残存する前記無機部材を除去する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)