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1. (WO2018101367) SEMICONDUCTOR SUBSTRATE
Latest bibliographic data on file with the International Bureau    Submit observation
Pub. No.: WO/2018/101367 International Application No.: PCT/JP2017/042919
Publication Date: 07.06.2018 International Filing Date: 29.11.2017
IPC:
H01L 21/205 (2006.01) ,C23C 16/34 (2006.01) ,C23C 16/42 (2006.01) ,H01L 21/338 (2006.01) ,H01L 29/778 (2006.01) ,H01L 29/812 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
20
Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
205
using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
C CHEMISTRY; METALLURGY
23
COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
C
COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
16
Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes
22
characterised by the deposition of inorganic material, other than metallic material
30
Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
34
Nitrides
C CHEMISTRY; METALLURGY
23
COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
C
COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
16
Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes
22
characterised by the deposition of inorganic material, other than metallic material
30
Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
42
Silicides
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
338
with a Schottky gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
778
with two-dimensional charge carrier gas channel, e.g. HEMT
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
80
with field effect produced by a PN or other rectifying junction gate
812
with a Schottky gate
Applicants:
住友化学株式会社 SUMITOMO CHEMICAL COMPANY, LIMITED [JP/JP]; 東京都中央区新川二丁目２７番１号 27-1, Shinkawa 2-chome, Chuo-ku, Tokyo 1048260, JP
Inventors:
山本　大貴 YAMAMOTO Taiki; JP
長田　剛規 OSADA Takenori; JP
Agent:
龍華国際特許業務法人 RYUKA IP LAW FIRM; 東京都新宿区西新宿１－６－１　新宿エルタワー２２階 22F, Shinjuku L Tower, 1-6-1, Nishi-Shinjuku, Shinjuku-ku, Tokyo 1631522, JP
Priority Data:
2016-23190230.11.2016JP
Title (EN) SEMICONDUCTOR SUBSTRATE
(FR) SUBSTRAT SEMICONDUCTEUR
(JA) 半導体基板
Abstract:
(EN) This semiconductor substrate comprises a silicon substrate, a reaction inhibition layer, a stress generation layer and an active layer, wherein the silicon substrate, the reaction inhibition layer, the stress generation layer and the active layer are positioned in the order of silicon substrate, reaction inhibition layer, stress generation layer and active layer. The reaction inhibition layer is a nitride crystal layer which inhibits the reaction between silicon atoms and group III atoms, the stress generation layer is a nitride crystal layer which generates compressive stress, and the active layer is a nitride crystal layer which forms an electronic element. The semiconductor substrate is further provided with a SiAlN layer having silicon atoms, aluminum atoms and nitrogen atoms as the main constituent elements thereof, between the silicon substrate and the reaction inhibition layer.
(FR) L'invention concerne un substrat semiconducteur comprenant un substrat de silicium, une couche d'inhibition de réaction, une couche de génération de contrainte et une couche active, le substrat de silicium, la couche d'inhibition de réaction, la couche de génération de contrainte et la couche active étant positionnées dans l'ordre du substrat de silicium, de la couche d'inhibition de réaction, de la couche de génération de contrainte et de la couche active. La couche d'inhibition de réaction est une couche de cristal de nitrure qui inhibe la réaction entre des atomes de silicium et des atomes de groupe III, la couche de génération de contrainte est une couche de cristal de nitrure qui génère une contrainte de compression, et la couche active est une couche de cristal de nitrure qui forme un élément électronique. Le substrat semiconducteur comprend en outre une couche de SiAlN ayant des atomes de silicium, des atomes d'aluminium et des atomes d'azote en tant qu'éléments constitutifs principaux de celui-ci, entre le substrat de silicium et la couche d'inhibition de réaction.
(JA) シリコン基板、反応抑制層、応力発生層および活性層を有し、シリコン基板、反応抑制層、応力発生層および活性層が、シリコン基板、反応抑制層、応力発生層、活性層の順に位置する半導体基板であって、反応抑制層が、シリコン原子とＩＩＩ族原子との反応を抑制する窒化物結晶層であり、応力発生層が、圧縮応力を発生する窒化物結晶層であり、活性層が、電子素子が形成される窒化物結晶層であり、シリコン基板と反応抑制層との間に、シリコン原子、アルミニウム原子および窒素原子を主構成原子とするＳｉＡｌＮ層をさらに有する半導体基板を提供する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)