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1. (WO2018101280) SEMICONDUCTOR SUBSTRATE
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/101280 International Application No.: PCT/JP2017/042694
Publication Date: 07.06.2018 International Filing Date: 28.11.2017
IPC:
H01L 21/205 (2006.01) ,C23C 16/30 (2006.01) ,C23C 16/34 (2006.01) ,H01L 21/338 (2006.01) ,H01L 29/778 (2006.01) ,H01L 29/812 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
20
Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
205
using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
C CHEMISTRY; METALLURGY
23
COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
C
COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
16
Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes
22
characterised by the deposition of inorganic material, other than metallic material
30
Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
C CHEMISTRY; METALLURGY
23
COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
C
COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
16
Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition (CVD) processes
22
characterised by the deposition of inorganic material, other than metallic material
30
Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
34
Nitrides
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
338
with a Schottky gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
778
with two-dimensional charge carrier gas channel, e.g. HEMT
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
80
with field effect produced by a PN or other rectifying junction gate
812
with a Schottky gate
Applicants:
住友化学株式会社 SUMITOMO CHEMICAL COMPANY, LIMITED [JP/JP]; 東京都中央区新川二丁目27番1号 27-1, Shinkawa 2-chome, Chuo-ku, Tokyo 1048260, JP
Inventors:
山本 大貴 YAMAMOTO Taiki; JP
長田 剛規 OSADA Takenori; JP
Agent:
龍華国際特許業務法人 RYUKA IP LAW FIRM; 東京都新宿区西新宿1-6-1 新宿エルタワー22階 22F, Shinjuku L Tower, 1-6-1, Nishi-Shinjuku, Shinjuku-ku, Tokyo 1631522, JP
Priority Data:
2016-23190130.11.2016JP
Title (EN) SEMICONDUCTOR SUBSTRATE
(FR) SUBSTRAT SEMI-CONDUCTEUR
(JA) 半導体基板
Abstract:
(EN) Provided is a semiconductor substrate comprises a buffer layer having a laminated structure obtained by repeatedly laminating a first crystal layer made from AlxGa1-xN and a second crystal layer made from AlyGa1-yN, and which, when the cross section of a buffer layer is subjected to TEM observation in an observation area including a single first crystal layer, the HAADF-STEM intensity I(D) which has depth D as a variable exhibits a minimum value Imin at a depth Dmin, and exhibits a maximum value Imax at a depth Dmax (Dmax>Dmin), and the distance in the depth direction DD1 from where I(D) is the median value Imid of Imax and Imin reaches Imin in the monotonically reducing region positioned more shallowly than Dmin, and the distance in the depth direction DD2 of I(D) from Imin to Imax in the monotonically increasing area positioned deeper than Dmin satisfy the condition DD1≤0.3×DD2.
(FR) La présente invention concerne un substrat semi-conducteur qui comprend une couche tampon ayant une structure stratifiée obtenue par stratification répétée d'une première couche de cristal composée d'AlxGa1-xN et d'une seconde couche de cristal composée d'AlyGa1-yN, et qui, lorsque la section transversale d'une couche tampon est soumise à une observation TEM dans une zone d'observation comprenant une seule première couche de cristal, l'intensité I(D) de STEM-HAADF qui a une profondeur D en tant que variable, présente une valeur minimale Imin, à une profondeur Dmin, et présente une valeur maximale Imax à une profondeur Dmax (Dmax > Dmin), et la distance dans la direction de profondeur DD1 à partir de l'endroit où I(D) représente la valeur médiane Imid d'Imax et où Imin atteint Imin dans la région diminuant de manière monotone positionnée plus superficiellement que Dmin, et la distance dans la direction de profondeur DD2 d'I(D) de l'Imin à Imax dans la zone augmentant de manière monotone positionnée plus profondément que Dmin satisfont la condition DD1 ≤ 0,3 × DD2.
(JA) AlGa1-xNからなる第1結晶層およびAlGa1-yNからなる第2結晶層が繰り返し積層された積層構造を有するバッファ層を有し、バッファ層の断面を単一の第1結晶層を含む観察領域においてTEM観察したとき、深さDを変数とするHAADF-STEM強度I(D)が、深さDminで極小値Iminを示し、深さDmax(Dmax>Dmin)で極大値Imaxを示し、Dminより浅く位置する単調減少領域においてI(D)がImaxおよびIminの中間値ImidからIminに至るまでの深さ方向距離DD1と、Dminより深く位置する単調増加領域においてI(D)がIminからImaxに至るまでの深さ方向距離DD2とが、DD1≦0.3× DD2、の条件を満たす半導体基板を提供する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)