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1. WO2018101275 - NEURAL NETWORK CIRCUIT DEVICE, NEURAL NETWORK, NEURAL NETWORK PROCESSING METHOD, AND NEURAL NETWORK EXECUTION PROGRAM

Publication Number WO/2018/101275
Publication Date 07.06.2018
International Application No. PCT/JP2017/042670
International Filing Date 28.11.2017
IPC
G06N 3/063 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3Computer systems based on biological models
02using neural network models
06Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
063using electronic means
CPC
G06N 3/04
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3Computer systems based on biological models
02using neural network models
04Architectures, e.g. interconnection topology
G06N 3/0445
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3Computer systems based on biological models
02using neural network models
04Architectures, e.g. interconnection topology
0445Feedback networks, e.g. hopfield nets, associative networks
G06N 3/0454
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3Computer systems based on biological models
02using neural network models
04Architectures, e.g. interconnection topology
0454using a combination of multiple neural nets
G06N 3/0481
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3Computer systems based on biological models
02using neural network models
04Architectures, e.g. interconnection topology
0481Non-linear activation functions, e.g. sigmoids, thresholds
G06N 3/063
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3Computer systems based on biological models
02using neural network models
06Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
063using electronic means
G06N 3/0635
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3Computer systems based on biological models
02using neural network models
06Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
063using electronic means
0635using analogue means
Applicants
  • 国立大学法人東京工業大学 TOKYO INSTITUTE OF TECHNOLOGY [JP]/[JP]
Inventors
  • 中原 啓貴 NAKAHARA Hiroki
  • 米川 晴義 YONEKAWA Haruyoshi
Agents
  • 特許業務法人磯野国際特許商標事務所 ISONO INTERNATIONAL PATENT OFFICE, P.C.
Priority Data
2016-23538302.12.2016JP
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) NEURAL NETWORK CIRCUIT DEVICE, NEURAL NETWORK, NEURAL NETWORK PROCESSING METHOD, AND NEURAL NETWORK EXECUTION PROGRAM
(FR) DISPOSITIF DE CIRCUIT DE RÉSEAU NEURONAL, RÉSEAU NEURONAL, PROCÉDÉ DE TRAITEMENT DE RÉSEAU NEURONAL ET PROGRAMME D'EXÉCUTION DE RÉSEAU NEURONAL
(JA) ニューラルネットワーク回路装置、ニューラルネットワーク、ニューラルネットワーク処理方法およびニューラルネットワークの実行プログラム
Abstract
(EN)
[Problem] To provide a neural network circuit device that does not require a batch normalization circuit, a neural network, a neural network processing method, and a neural network execution program. [Solution] A binary neural network circuit (100) is provided with an input node for inputting input values x1-xn (xi) (binary) and an input unit (101) for inputting weights w1-wn (wi), an XNOR gate circuit (102) for receiving the input values x1-xn and weights w1-wn and taking the XNOR logic thereof, a multibit bias W' input unit (110) for inputting a multibit bias W', a summing circuit (103) for taking the sum total of each XNOR logic value and the multibit bias W', and an activation circuit (120) for outputting only a sign bit for a signal Y derived by summation.
(FR)
Le problème décrit par la présente invention est de fournir un dispositif de circuit de réseau neuronal qui ne nécessite pas de circuit de normalisation de lot, un réseau neuronal, un procédé de traitement de réseau neuronal et un programme d'exécution de réseau neuronal. La Solution selon l'invention porte sur un circuit de réseau neuronal binaire (100) qui est pourvu d'un nœud d'entrée pour entrer des valeurs d'entrée x1-xn (xi) (binaire) et d'une unité d'entrée (101) pour entrer des poids w1-wn (wi), un circuit de porte XNOR (102) pour recevoir les valeurs d'entrée x1-xn et les poids w1-wn et prendre la logique XNOR de celui-ci, une unité d'entrée W' de biais multibit (110) pour entrer un biais multibit W', un circuit de sommation (103) pour prendre la somme totale de chaque valeur logique XNOR et du biais multibit W', et un circuit d'activation (120) pour délivrer uniquement un bit de signe pour un signal Y issu de la sommation.
(JA)
【課題】バッチ正規化回路が不要なニューラルネットワーク回路装置、ニューラルネットワーク、ニューラルネットワーク処理方法およびニューラルネットワークの実行プログラムを提供する。 【解決手段】2値化ニューラルネットワーク回路(100)は、入力値x1~xn(xi)(2値)を入力する入力ノードおよび重みw1~wn(wi)を入力する入力部(101)と、入力値x1~xnおよび重みw1~wnを受け取り、XNOR論理を取るXNORゲート回路(102)と、多ビットバイアスW'を入力する多ビットバイアスW'入力部(110)と、各XNOR論理値と多ビットバイアスW'との総和を取る総和回路(103)と、総和を取った信号Yに対して符号ビットのみを出力する活性化回路(120)と、を備える。
Also published as
EP2017875690
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