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1. (WO2018101159) CONNECTION WIRING

Pub. No.:    WO/2018/101159    International Application No.:    PCT/JP2017/042167
Publication Date: Fri Jun 08 01:59:59 CEST 2018 International Filing Date: Sat Nov 25 00:59:59 CET 2017
IPC: G09F 9/30
G02F 1/1345
G09F 9/00
Applicants: SHARP KABUSHIKI KAISHA
シャープ株式会社
Inventors: MURAOKA, Seiji
村岡 盛司
SHIMIZU, Yukio
清水 行男
SHIOTA, Motoji
塩田 素二
Title: CONNECTION WIRING
Abstract:
Provided is connection wiring which suppresses faulty connections between pumps and pads when mounting semiconductor chips, and allows for an increase in the number of pads. In a region sandwiched by a pad row at a particular level and a pad row at a level adjacent to said level, the connection wiring is arranged such that a first wire 31 goes beneath a second wire 32 which is adjacent thereto, and the second wire 32 goes above the first wire 31 which is adjacent thereto. In this case, of the three wires, the wire located in the middle is the first wire 31, and the second wire 32 is disposed so as to sandwich the first wire 31, even in a region sandwiched by pads 20 at any level. The pitch of the pads 20 can thus be made narrower without reducing the width of the pads.