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1. (WO2018100647) GATE DRIVING CIRCUIT
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Pub. No.: WO/2018/100647 International Application No.: PCT/JP2016/085424
Publication Date: 07.06.2018 International Filing Date: 29.11.2016
IPC:
H03K 17/567 (2006.01) ,H02M 1/08 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
K
PULSE TECHNIQUE
17
Electronic switching or gating, i.e. not by contact-making and -breaking
51
characterised by the use of specified components
56
by the use, as active elements, of semiconductor devices
567
Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
H ELECTRICITY
02
GENERATION, CONVERSION, OR DISTRIBUTION OF ELECTRIC POWER
M
APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
1
Details of apparatus for conversion
08
Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
Applicants: MITSUBISHI ELECTRIC CORPORATION[JP/JP]; 7-3, Marunouchi 2-chome, Chiyoda-ku, Tokyo 1008310, JP
Inventors: SAITO, Shota; JP
NAKAMOTO, Keisuke; JP
Agent: TAKADA, Mamoru; JP
TAKAHASHI, Hideki; JP
Priority Data:
Title (EN) GATE DRIVING CIRCUIT
(FR) CIRCUIT D'ATTAQUE DE GRILLE
(JA) ゲート駆動回路
Abstract:
(EN) According to the present invention, a plurality of gate driver units (3, 4) respectively drive a plurality of semiconductor switching elements (SW1, SW2) connected in parallel. A control circuit (5) controls the plurality of gate driver units (3, 4). The gate driver units (3, 4) each have: a gate driver (6) that supplies a gate voltage to gates of the corresponding semiconductor switching elements (SW1, SW2); and a potential difference measuring unit (7) that measures, for each cycle of an output frequency, a potential difference (Va) generated by a wire inductance on an emitter side of the corresponding semiconductor switching elements (SW1, SW2). The control circuit (5) adjusts the gate voltage (VGE), supplied by the gate driver (6) of each of the gate driver units (3, 4), such that potential differences (Va) of the plurality of semiconductor switching elements (SW1, SW2) during a turn-on or turn-off switching operation are equal to each other.
(FR) Selon la présente invention, une pluralité d'unités d'attaque de grille (3, 4) excitent respectivement une pluralité d'éléments de commutation à semi-conducteur (SW1, SW2) montés en dérivation. Un circuit de commande (5) commande la pluralité d'unités d'attaque de grille (3, 4). Chacune des unités d'attaque de grille (3, 4) comprend : un circuit d'attaque de grille (6) qui fournit une tension de grille aux grilles des éléments de commutation à semi-conducteur correspondants (SW1, SW2) ; et une unité de mesure de différence de potentiel (7) qui mesure, pour chaque cycle d'une fréquence de sortie, une différence de potentiel (Va) générée par une inductance de fil sur un côté émetteur des éléments de commutation à semi-conducteur correspondants (SW1, SW2). Le circuit de commande (5) règle la tension de grille (VGE), fournie par le circuit d'attaque de grille (6) de chacune des unités d'attaque de grille (3, 4), de telle sorte que les différences de potentiel (Va) de la pluralité d'éléments de commutation à semi-conducteur (SW1, SW2) pendant une opération de commutation de mise sous tension ou de mise hors tension sont égales l'une à l'autre.
(JA) 複数のゲートドライバユニット(3,4)が、並列に接続された複数の半導体スイッチング素子(SW1,SW2)をそれぞれ駆動する。制御回路(5)が複数のゲートドライバユニット(3,4)を制御する。ゲートドライバユニット(3,4)は、対応する半導体スイッチング素子(SW1,SW2)のゲートにゲート電圧を供給するゲートドライバ(6)と、対応する半導体スイッチング素子(SW1,SW2)のエミッタ側の配線インダクタンスにより発生する電位差(Va)を出力周波数の1周期ごとに測定する電位差測定部(7)とを有する。制御回路(5)は、ターンオン又はターンオフのスイッチング動作時の複数の半導体スイッチング素子(SW1,SW2)の電位差(Va)が互いに同じになるように、各ゲートドライバユニット(3,4)のゲートドライバ(6)が供給するゲート電圧(VGE)を調整する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)