Search International and National Patent Collections

1. (WO2018100456) MEMORY ACCESS CONTROL FOR PARALLELIZED PROCESSING

Pub. No.:    WO/2018/100456    International Application No.:    PCT/IB2017/057122
Publication Date: Fri Jun 08 01:59:59 CEST 2018 International Filing Date: Thu Nov 16 00:59:59 CET 2017
IPC: G06F 9/30
G06F 9/38
Applicants: CENTIPEDE SEMI LTD.
Inventors: LEVISON, Nadav
MIZRAHI, Noam
Title: MEMORY ACCESS CONTROL FOR PARALLELIZED PROCESSING
Abstract:
A processor (20) includes a hardware-implemented pipeline and parallelization circuitry. The pipeline processes program code. The parallelization circuitry creates a first (earlier) segment and a second (later) segment of the program code to be processed in parallel. Each segment is an ordered sequence of instructions within the program code. A last store to a memory address is identified in the first segment. During parallelized processing of the first segment and the second segment, the parallelization circuitry controls second segment loads which are potentially dependent on the last store by: during processing of the first segment instructions, providing a release notification when the memory address is available for subsequent instructions, and, during processing of the second segment instructions, issuing a second segment load which is potentially dependent on the last store for execution after the release notification is provided.