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1. (WO2018100363) MEMORY ADDRESS TRANSLATION

Pub. No.:    WO/2018/100363    International Application No.:    PCT/GB2017/053588
Publication Date: Fri Jun 08 01:59:59 CEST 2018 International Filing Date: Thu Nov 30 00:59:59 CET 2017
IPC: G11C 11/408
G11C 8/06
G06F 12/1027
Applicants: ARM LIMITED
Inventors: NIKOLERIS, Nikos
SANDBERG, Andreas Lars
RAMRAKHYANI, Prakash S.
DIESTELHORST, Stephan
Title: MEMORY ADDRESS TRANSLATION
Abstract:
Memory address translation apparatus comprises page table access circuitry to access a page table to retrieve translation data defining an address translation between an initial memory address in an initial memory address space, and a corresponding output memory address in an output address space; a translation data buffer to store, for a subset of the initial address space, one or more instances of the translation data; the translation data buffer comprising: an array of storage locations arranged in rows and columns; a row buffer comprising a plurality of entries each to store information from a respective portion of a row of the array; and comparison circuitry responsive to a key value dependent upon at least the initial memory address, to compare the key value with information stored in each of at least one key entry of the row buffer, each key entry having an associated value entry for storing at least a representation of a corresponding output memory address, and to identify which of the at least one key entry, if any, is a matching key entry storing information matching the key value; and output circuitry to output, when there is a matching key entry, at least the representation of the output memory address in the value entry associated with the matching key entry.