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1. (WO2018099908) SEMICONDUCTOR PATTERNING
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/099908 International Application No.: PCT/EP2017/080649
Publication Date: 07.06.2018 International Filing Date: 28.11.2017
IPC:
H01L 51/40 (2006.01) ,H01L 51/05 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
51
Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
05
specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier
40
Processes or apparatus specially adapted for the manufacture or treatment of such devices or of parts thereof
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
51
Solid state devices using organic materials as the active part, or using a combination of organic materials with other materials as the active part; Processes or apparatus specially adapted for the manufacture or treatment of such devices, or of parts thereof
05
specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier
Applicants: FLEXENABLE LIMITED[GB/GB]; 34 Cambridge Science Park Milton Road Cambridge CB4 0FX, GB
Inventors: JONGMAN, Jan; GB
ASPLIN, Brian; GB
Agent: MARC NIGEL EVANS; PAGE WHITE & FARRER Bedford House John Street London Greater London WC1N 2BF, GB
Priority Data:
1620223.629.11.2016GB
Title (EN) SEMICONDUCTOR PATTERNING
(FR) MODELAGE DE CONTOURS DE SEMI-CONDUCTEUR
Abstract:
(EN) A technique of producing a stack defining a plurality of TFTs including at least source/drain electrodes and addressing lines at a source/drain level, wherein the method comprises: forming a patterned source/drain level stack comprising at least a first layer over the support substrate and a second layer over the first layer, to define at least said source/drain electrodes and said addressing lines; depositing semiconductor channel material over at least said source/drain electrodes and said addressing lines; and patterning the layer of semiconductor channel material by a patterning process; wherein the material of the first layer is more resistant to removal by said patterning process than the material of said second layer.
(FR) La présente invention concerne une technique de production d'un empilement définissant une pluralité de transistors à couches minces (TFT) comprenant au moins des électrodes source/drain et des lignes d'adressage à un niveau source/drain, le procédé consistant à : former un empilement de niveaux de source/drain à motifs comprenant au moins une première couche sur le substrat de support et une seconde couche sur la première couche, pour définir au moins lesdites électrodes source/drain et lesdites lignes d'adressage ; déposer un matériau de canal semi-conducteur sur au moins lesdites électrodes source/drain et lesdites lignes d'adressage ; modeler des contours sur la couche de matériau de canal semi-conducteur par un procédé de modelage de contours ; le matériau de la première couche étant plus résistant à l'élimination par ledit processus de modelage de contours que le matériau de ladite seconde couche.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)