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1. (WO2018099304) SYSTEM AND METHOD FOR REGULATING TRANSFER CHARACTERISTICS OF INTEGRAL DIGITAL-TO-ANALOG CONVERTER

Pub. No.:    WO/2018/099304    International Application No.:    PCT/CN2017/112352
Publication Date: Fri Jun 08 01:59:59 CEST 2018 International Filing Date: Thu Nov 23 00:59:59 CET 2017
IPC: H03M 1/52
Applicants: SHANGHAI IC R & D CENTER CO., LTD.
上海集成电路研发中心有限公司
CHENGDU IMAGE DESIGN TECHNOLOGY CO. LTD.
成都微光集电科技有限公司
Inventors: HE, Xuehong
何学红
PI, Changming
皮常明
YANG, Hailing
杨海玲
Title: SYSTEM AND METHOD FOR REGULATING TRANSFER CHARACTERISTICS OF INTEGRAL DIGITAL-TO-ANALOG CONVERTER
Abstract:
Disclosed are a system and method for regulating transfer characteristics of an integral analog-to-digital converter (ADC). The system is provided with a cascaded N-level integrator structure constituted by N integrators, an output end of each integrator is connected to an input end of the integrator adjacent thereto, the input end of the first integrator is connected to an input voltage, the output end of the N-th integrator is connected to an output node (VRAMP), where N is a positive integer greater than or equal to 2; and in the cascaded N-level integrators, changes in the voltage of the output node (VRAMP) are directly proportional to the N-th power of time. The present invention utilizes cascaded multilevel integrators of a simple implementation scheme, facilitates subsequent digital signal processing, reduces the conversion time of the ADC, and increases the conversion rate of the ADC; compared with an existing polyline approach, the present invention is of an improved linearity and is easy to expand to cascaded multilevel integrators.