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1. (WO2018099066) METHOD OF FABRICATING THIN FILM TRANSISTOR, THIN FILM TRANSISTOR, AND DISPLAY APPARATUS
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Pub. No.: WO/2018/099066 International Application No.: PCT/CN2017/091081
Publication Date: 07.06.2018 International Filing Date: 30.06.2017
IPC:
H01L 21/336 (2006.01) ,H01L 29/423 (2006.01) ,H01L 21/34 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
41
characterised by their shape, relative sizes or dispositions
423
not carrying the current to be rectified, amplified or switched
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
34
the devices having semiconductor bodies not provided for in groups H01L21/06, H01L21/16, and H01L21/18159
Applicants:
BOE TECHNOLOGY GROUP CO., LTD. [CN/CN]; No.10 Jiuxianqiao Rd., Chaoyang District Beijing 100015, CN
Inventors:
SONG, Zhen; CN
LI, Wei; CN
WANG, Guoying; CN
Agent:
TEE & HOWE INTELLECTUAL PROPERTY ATTORNEYS; Yuan CHEN 10th Floor, Tower D, Minsheng Financial Center, 28 Jianguomennei Avenue, Dongcheng District Beijing 100005, CN
Priority Data:
201611082799.930.11.2016CN
Title (EN) METHOD OF FABRICATING THIN FILM TRANSISTOR, THIN FILM TRANSISTOR, AND DISPLAY APPARATUS
(FR) PROCÉDÉ DE FABRICATION D'UN TRANSISTOR À COUCHES MINCES, TRANSISTOR À COUCHES MINCES ET APPAREIL D'AFFICHAGE
Abstract:
(EN) A thin film transistor and a fabricating method thereof are provided. The method includes: forming an active layer (1) having a channel region (R3), a source electrode contact region (R1), and a drain electrode contact region (R2), on a base substrate (10); forming a first photoresist layer (20) on a side of the active layer (1) distal to the base substrate (10), the first photoresist layer (20) is formed in a region outside that corresponding to the channel region (R3); forming an insulating material layer (102) on a side of the first photoresist layer (20) distal to the base substrate (10); forming a first conductive metal material layer (202) on a side of the insulating material layer (102) distal to the first photoresist layer (20), and removing the first photoresist layer (20), the insulating material layer (102), the first conductive metal material layer (202), in the region outside that corresponding to the channel region (R3) by a lift-off method.
(FR) L'invention concerne un transistor à couches minces et son procédé de fabrication. Le procédé consiste à : former une couche active (1) ayant une région de canal (R3), une région de contact d'électrode de source (R1) et une région de contact d'électrode de drain (R2), sur un substrat de base (10); former une première couche de résine photosensible (20) sur un côté de la couche active (1) distal par rapport au substrat de base (10), la première couche de résine photosensible (20) étant formée dans une région à l'extérieur de celle correspondant à la région de canal (R3); former une couche de matériau isolant (102) sur un côté de la première couche de résine photosensible (20) distal par rapport au substrat de base (10); former une première couche de matériau métallique conducteur (202) sur un côté de la couche de matériau isolant (102) distal par rapport à la première couche de résine photosensible (20); et retirer la première couche de résine photosensible (20), la couche de matériau isolant (102), la première couche de matériau métallique conducteur (202), dans la région à l'extérieur de celle correspondant à la région de canal (R3) par un procédé de décollement.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)