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1. (WO2018098922) CHIP WIRING METHOD AND STRUCTURE
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Pub. No.: WO/2018/098922 International Application No.: PCT/CN2017/076430
Publication Date: 07.06.2018 International Filing Date: 13.03.2017
IPC:
H05K 1/00 (2006.01)
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1
Printed circuits
Applicants:
深圳修远电子科技有限公司 SHENZHEN XIUYUAN ELECTRONIC TECHNOLOGY CO., LTD [CN/CN]; 中国广东省深圳市 南山区蛇口街道沿山路18号中建工业大厦2栋6楼601 Room 601, Building 2, Zhongjian Industrial Building, No.18 Yanshan Road, Shekou Street, Nanshan District Shenzhen, Guangdong 518067, CN
Inventors:
胡川 HU, Chuan; US
刘俊军 LIU, Junjun; US
Agent:
广州番禺容大专利代理事务所(普通合伙) GUANGZHOU PANYU RONDA PATENT AGENCY; 中国广东省广州市 越秀区东风中路300号之一金安大厦14楼B室 Room B, Floor 14, JinAn Building, No. 300, Dong Feng Zhong Road, Yuexiu District Guangzhou, Guangdong 510030, CN
Priority Data:
PCT/CN2016/10783329.11.2016CN
Title (EN) CHIP WIRING METHOD AND STRUCTURE
(FR) PROCÉDÉ ET STRUCTURE DE CÂBLAGE DE PUCE
(ZH) 芯片连线方法及结构
Abstract:
(EN) A chip (201) wiring method and structure, the chip (201) wiring method comprising: a substrate (100) being provided with with a first connecting wire (111b) and a second connecting wire (111a, 111c), wherein, on the thickness direction of the substrate (100), a distance between the first connecting wire (111b) and the chip (201) is smaller than a distance between the second connecting wire (111a, 111c) and the chip (201); providing the chip (201) on a top surface of the substrate (100), the chip (201) being provided with at least two chip pins (211a, 211b, 211c); providing the substrate (100) with a second through hole (121a, 121c), the second through hole (121a, 121c) corresponding to the second connecting wire (111a, 111c), and the second through hole (121a, 121c) being provided therein with a second conductive layer (401a, 401c); at least one chip pin (211a, 211b, 211c) being electrically connected to the first connecting wire (111b), and at least another chip pin (211a, 211b, 211c) corresponding to a first opening (120c) of the second through hole (121a, 121c), and the second conductive layer (401a, 401c) electrically connecting the chip pin (211a, 211b, 211c) and the second connecting wire (111a, 111c). The wiring bypasses a shielding of the chip pin (211a, 211b, 211c), which may obtain a high-density chip pin (211a, 211b, 211c) and a connecting wire, thereby increasing the number of nodes connected to the chip (201) and increasing data transfer speed of the chip (201).
(FR) L'invention concerne un procédé et une structure de câblage de puce (201), le procédé de câblage de puce (201) consistant à : utiliser un substrat (100) qui est pourvu d'un premier fil de connexion (111b) et d'un second fil de connexion (111a, 111c), la distance entre le premier fil de connexion (111b) et la puce (201) étant, dans le sens de l'épaisseur du substrat (100), inférieure à la distance entre le second fil de connexion (111a, 111c) et la puce (201); fournir la puce (201) sur une surface supérieure du substrat (100), la puce (201) étant pourvue d'au moins deux broches de puce (211a, 211b, 211c); fournir le substrat (100) avec un second trou traversant (121a, 121c), le second trou traversant (121a, 121c) correspondant au second fil de connexion (111a, 111c), et le second trou traversant (121a, 121c) étant pourvu en son sein d'une seconde couche conductrice (401a, 401c); au moins une broche de puce (211a, 211b, 211c) étant électriquement connectée au premier fil de connexion (111b), et au moins une autre broche de puce (211a, 211b, 211c) correspondant à une première ouverture (120c) du second trou traversant (121a, 121c), et la seconde couche conductrice (401a, 401c) connectant électriquement la broche de puce (211a, 211b, 211c) et le second fil de connexion (111a, 111c). Le câblage contourne un blindage de la broche de puce (211a, 211b, 211c), qui peut obtenir une broche de puce haute densité (211a, 211b, 211c) et un fil de connexion, ce qui permet d'augmenter le nombre de nœuds connectés à la puce (201) et d'augmenter la vitesse de transfert de données de la puce (201).
(ZH) 一种芯片(201)连线方法及结构,其中芯片(201)连线方法包括:所述基板(100)设有第一连线(111b)和第二连线(111a、111c),在所述基板(100)的厚度方向上,所述第一连线(111b)与所述芯片(201)的距离小于所述第二连线(111a、111c)与所述芯片(201)的距离,将芯片(201)设于所述基板(100)的顶面,所述芯片(201)设有至少两个芯片引脚(211a、211b、211c),所述基板(100)设有第二通孔(121a、121c),所述第二通孔(121a、121c)与所述第二连线(111a、111c)对应,所述第二通孔(121a、121c)内设有第二导电层(401a、401c);其中,至少一个所述芯片引脚(211a、211b、211c)与所述第一连线(111b)电连接,另有至少一个所述芯片引脚(211a、211b、211c)与所述第二通孔(121a、121c)的第一开口(120c)对应、并且所述第二导电层(401a、401c)将所述芯片引脚(211a、211b、211c)与所述第二连线(111a、111c)电连接。连线绕过芯片引脚(211a、211b、211c)的遮挡,可以获得高密度的芯片引脚(211a、211b、211c)、连线,提高芯片(201)连接的节点数量,提高芯片(201)数据传输速度。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)