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1. (WO2018098648) INTEGRATED CIRCUIT PACKAGING METHOD AND INTEGRATED PACKAGING CIRCUIT

Pub. No.:    WO/2018/098648    International Application No.:    PCT/CN2016/107832
Publication Date: Fri Jun 08 01:59:59 CEST 2018 International Filing Date: Thu Dec 01 00:59:59 CET 2016
IPC: H01L 23/498
Applicants: SHENZHEN XIUYUAN ELECTRONIC TECHNOLOGY CO., LTD
深圳修远电子科技有限公司
Inventors: HU, Chuan
胡川
LIU, Junjun
刘俊军
GUO, Yuejin
郭跃进
PRACK, Edward Rudolph
普莱克爱德华⋅鲁道夫
Title: INTEGRATED CIRCUIT PACKAGING METHOD AND INTEGRATED PACKAGING CIRCUIT
Abstract:
An integrated circuit packaging method and an integrated packaging circuit, the integrated circuit packaging method comprising: circuit layers (110a, 110b) are provided on the top surface of a substrate (100), the bottom surface of the substrate (100) or the interior of the substrate (100), the circuit layers (110a, 110b) having circuit pins; the substrate (100) is provided with connection through holes (120a, 120b), and the connection through holes (120a, 120b) are joined up with the circuit pins; a component (200) is placed on the substrate (100), and the component ( 200) is provided with component pins (210a, 210b) on a surface facing the substrate (100), which makes the component pins (210a, 210b) join up with a first opening (120c) of the connection through holes (120a, 120b); conductive layers (400a, 400b) are fabricated in the connection through holes (120a, 120b) by means of a second opening (120d) of the connection through holes (120a, 120b); and the conductive layers (400a, 400b) electrically connect the component pins (210a, 210b) to the circuit pins. Said fabrication process is simple, cost is low, and the volume of an integrated packaged circuit is reduced while the reliability thereof is improved.