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1. (WO2018098647) INTEGRATED CIRCUIT MULTICHIP STACKED PACKAGING STRUCTURE AND METHOD

Pub. No.:    WO/2018/098647    International Application No.:    PCT/CN2016/107831
Publication Date: Fri Jun 08 01:59:59 CEST 2018 International Filing Date: Thu Dec 01 00:59:59 CET 2016
IPC: H01L 21/50
Applicants: SHENZHEN XIUYUAN ELECTRONIC TECHNOLOGY CO., LTD
深圳修远电子科技有限公司
Inventors: HU, Chuan
胡川
LIU, Junjun
刘俊军
GUO, Yuejin
郭跃进
PRACK, Edward Rudolph
普莱克爱德华⋅鲁道夫
Title: INTEGRATED CIRCUIT MULTICHIP STACKED PACKAGING STRUCTURE AND METHOD
Abstract:
The present invention relates to an integrated circuit multichip stacked packaging structure and method. The integrated circuit multichip stacked packaging structure comprises: a first pin is provided at the bottom surface of a first chip; a second pin is provided at the top surface of a second chip; a circuit layer is provided at the top surface of a substrate, and/or a circuit layer is provided at the bottom surface of the substrate, and/or a circuit layer is provided within the substrate; the first chip is provided at the top surface of the substrate; the second chip is provided at the top surface of the first chip; the first pin is electrically connected at least to one of the circuit layers: the circuit layer is provided with a circuit pin, the substrate is provided with a connecting through hole, the connecting through hole is docked with the circuit pin, a first opening of the connecting through hole is docked with the first pin, a second opening of the connecting through hole is an operating window, an electrically-conductive layer is provided within the connecting through hole, and the electrically-conductive layer electrically connects the first pin to the circuit pin; the second pin is electrically connected at least to one of the circuit layers: the second pin is electrically connected to the circuit layer via the electrically-conductive layer. The connections of the chips to the circuit layers are of high density and compact size.