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1. (WO2018093515) MICROELECTRONIC DEVICE PACKAGE HAVING ALTERNATELY STACKED DIE
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Claims

1. A microelectronic device, comprising:

a substrate;

first and second semiconductor die supported by the substrate in

laterally spaced relation to one another defining a first gap extending in a first direction;

third and fourth semiconductor die extending over the first and second semiconductor die and in laterally spaced relation to one another defining a second gap extending in a second direction angularly offset from the first direction of the first gap.

2. The microelectronic device of claim 1, wherein the second gap extends perpendicular to the first gap.

3. The microelectronic device of claim 1, wherein the first and second semiconductor die are directly connected to the substrate.

4. The microelectronic device of claim 1, wherein the third and fourth semiconductor die each extend across and is connected to each of said first and second die.

5. The microelectronic device of claim 1, further comprising fifth and sixth semiconductor die extending over the third and fourth semiconductor die and in laterally spaced relation to one another defining a third gap extending in a third direction angularly offset from at least one of the first and second directions.

6. The microelectronic device of claim 5, wherein the third direction and the first direction are the same.

7. The microelectronic device of claim 1, wherein one of the first and second gaps extends vertically adjacent a thermally active region of at least one die.

8. The microelectronic device of any of claims 1-7, wherein at least one die includes multiple vertical interconnects electrically coupling respective contacts of another die above such die, to contacts extending below such die.

9. The microelectronic device of claim 8, wherein the multiple vertical interconnects comprise multiple through-silicon vias.

10. The microelectronic device of any of claims 1-7, wherein the substrate is the package substrate.

11. The microelectronic device of any of claims 1-7, wherein one die is a processor.

12. The microelectronic device of any of claims 1-7, wherein at least one die is a memory device.

13. The microelectronic device of any of claims 1-7, wherein at least one of the die is a bridge device providing interconnects between at least two other die.

14. A method of manufacturing a microelectronic device, comprising:

attaching multiple semiconductor die to a substrate to form a base layer of die, the multiple die of the base layer arranged in a first orientation, wherein the multiple die are in laterally spaced relation to one another to define at least one gap extending in a first direction;

attaching multiple semiconductor die to the multiple die of the base layer to form a second layer of die, the multiple die of the second layer arranged in a second orientation, wherein the multiple die are in laterally spaced relation to one another to define at least one gap extending in a second direction angularly offset from the first direction.

15. The method of claim 14, further comprising applying a retention material to at least some die of the multiple semiconductor die of each of the first and second layers.

16. The method of any of claims 14-15, wherein the second direction is perpendicular to the first direction.

17. The method of any of claims 14-15, further comprising attaching

multiple semiconductor die to the multiple die of the second layer to form a third layer of die, the multiple die of the third layer arranged in laterally spaced relation to one another to define at least one gap extending in the first direction.

18. The method of any of claims 14-15, wherein at least one of the gaps formed between die in a layer extends adjacent a thermally active region of at least one die in an adjacent layer.

19. The method of claim 18, wherein the thermally active region is a region of a processor.

20. The method of any of claims 14-15, wherein at least one die includes multiple vertical interconnects electrically coupling respective contacts of another die in a layer above the at least one die, to contacts extending below the at least one die.

21. The method of claim 20, wherein attaching the multiple die of the second layer to the multiple die of the first layer comprises establishing an electrical connection between at least one die of the second layer and the substrate through vertical interconnects in at least one die of the base layer.

22. An electronic system, comprising:

a microelectronic device, comprising,

a substrate,

a first semiconductor die layer including first and second semiconductor die supported by the substrate in laterally spaced relation to one another defining a first gap extending in a first direction, a second semiconductor die layer including third and fourth

semiconductor die extending over the first and second semiconductor die and in laterally spaced relation to one another defining a second gap extending in a second direction perpendicular to the first direction of the first gap; and at least one of a mass storage device and a network interface operably coupled to the microelectronic device.

23. The electronic system of claim 22, wherein the first and second

semiconductor die are coupled directly to the substrate.

24. The electronic system of any of claims 22-23, further comprising:

a third semiconductor die layer including fifth and sixth semiconductor die extending over the third and fourth semiconductor die and in laterally spaced relation to one another defining a third gap extending in the first direction.

25. The electronic system of any of claims 22-23, wherein one of the

defined gaps in one of the layers extends adjacent a thermally active region of at least one die in a vertically adjacent layer.