WIPO logo
Mobile | Deutsch | Español | Français | 日本語 | 한국어 | Português | Русский | 中文 | العربية |
PATENTSCOPE

Search International and National Patent Collections
World Intellectual Property Organization
Search
 
Browse
 
Translate
 
Options
 
News
 
Login
 
Help
 
Machine translation
1. (WO2018089936) RRAM PROCESS INTERGRATION SCHEME AND CELL STRUCTURE WITH REDUCED MASKING OPERATIONS
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.:    WO/2018/089936    International Application No.:    PCT/US2017/061393
Publication Date: 17.05.2018 International Filing Date: 13.11.2017
IPC:
G11C 11/56 (2006.01), G11C 7/12 (2006.01), G11C 13/00 (2006.01), H01L 27/24 (2006.01), H01L 27/02 (2006.01), H01L 45/00 (2006.01)
Applicants: RAMBUS INC. [US/US]; 1050 Enterprise Way, Suite 700 Sunnyvale, California 94089 (US)
Inventors: LU, Zhichao; (US).
HAUKNESS, Brent Steven; (US)
Agent: PORTNOVA, Marina; (US)
Priority Data:
62/421,779 14.11.2016 US
62/490,222 26.04.2017 US
Title (EN) RRAM PROCESS INTERGRATION SCHEME AND CELL STRUCTURE WITH REDUCED MASKING OPERATIONS
(FR) SCHÉMA D'INTÉGRATION DE PROCESSUS RRAM ET STRUCTURE DE CELLULE AVEC DES OPÉRATIONS DE MASQUAGE RÉDUITES
Abstract: front page image
(EN)Disclosed is a resistive random access memory (RRAM). The RRAM includes a bottom electrode made of tungsten and a switching layer made of hafnium oxide disposed above the bottom electrode, wherein the switching layer includes a switchable filament. The RRAM further includes a resistive layer disposed above the switching layer and a bit line disposed above the resistive layer, wherein the resistive layer extends laterally to connect two or more memory cells along the bit line.
(FR)L'invention concerne une mémoire vive résistive (RRAM). La RRAM comprend une électrode inférieure en tungstène et une couche de commutation en oxyde d'hafnium disposée au-dessus de l'électrode inférieure, la couche de commutation comprenant un filament commutable. La RRAM comprend en outre une couche résistive disposée au-dessus de la couche de commutation et une ligne de bits disposée au-dessus de la couche résistive, la couche résistive s'étendant latéralement pour relier deux cellules de mémoire ou plus le long de la ligne de bits.
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW.
African Regional Intellectual Property Organization (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG).
Publication Language: English (EN)
Filing Language: English (EN)