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1. (WO2018088373) BIAS CIRCUIT AND AMPLIFICATION APPARATUS

Pub. No.:    WO/2018/088373    International Application No.:    PCT/JP2017/039992
Publication Date: Fri May 18 01:59:59 CEST 2018 International Filing Date: Tue Nov 07 00:59:59 CET 2017
IPC: H03F 3/345
H03F 3/45
Applicants: TOHOKU UNIVERSITY
国立大学法人東北大学
Inventors: TANOI Satoru
田野井 聡
ENDOH Tetsuo
遠藤 哲郎
Title: BIAS CIRCUIT AND AMPLIFICATION APPARATUS
Abstract:
Provided are a bias circuit that can supply a bias voltage for suppressing the influence of process fluctuation on an amplification circuit, and an amplification apparatus that uses the bias circuit. A bias circuit 11 is provided with: a first voltage output unit 14; a second voltage output unit 15; and a voltage comparator 16. The first voltage output unit 14 comprises a first current source 21 and a transistor P111 that are connected in series. The first current source 21 increases/decreases a current according to a bias voltage Vq outputted from the voltage comparator 16. The second voltage output unit 15 comprises a second current source 22 and a transistor N111 that are connected in series, and the second current source 22 supplies a constant current. The voltage comparator 16 compares drain voltages of the diode-connected transistors P111, N111 with each other, and sets the drain voltages equal to each other by increasing/decreasing the bias voltage Vq according to the result of the comparison. The bias voltage Vq is supplied to an amplification circuit 12. The amplification circuit 12 has: a source follower stage 17 that includes a p-type MOSFET; and an amplification stage 18 that includes an n-type MOSFET.