WIPO logo
Mobile | Deutsch | Español | Français | 日本語 | 한국어 | Português | Русский | 中文 | العربية |
PATENTSCOPE

Search International and National Patent Collections
World Intellectual Property Organization
Options
Query Language
Stem
Sort by:
List Length
Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2018087899) MOSFET AND POWER CONVERSION CIRCUIT
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/087899 International Application No.: PCT/JP2016/083610
Publication Date: 17.05.2018 International Filing Date: 11.11.2016
IPC:
H01L 29/78 (2006.01) ,H01L 27/04 (2006.01) ,H01L 29/12 (2006.01) ,H02M 1/00 (2007.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
12
characterised by the materials of which they are formed
H ELECTRICITY
02
GENERATION, CONVERSION, OR DISTRIBUTION OF ELECTRIC POWER
M
APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
1
Details of apparatus for conversion
Applicants: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD.[JP/JP]; 2-1, Ohtemachi 2-chome, Chiyoda-ku, Tokyo 1000004, JP
Inventors: ARAI, Daisuke; JP
KITADA, Mizue; JP
Agent: MATSUO, Nobutaka; JP
Priority Data:
Title (EN) MOSFET AND POWER CONVERSION CIRCUIT
(FR) MOSFET ET CIRCUIT CONVERTISSEUR DE PUISSANCE
(JA) MOSFET及び電力変換回路
Abstract:
(EN) This MOSFET 100 is characterized by being provided with: a semiconductor substrate 110 which is provided with an n-type column region 114, a p-type column region 116, a base region 118, and a source region 120, and in which a super junction structure is formed by the n-type column region 114 and the p-type column region 116; a trench 122 which is provided with side walls and a bottom; a gate electrode 126 formed in the trench 122 with a gate insulating film 124 therebetween; a carrier compensation electrode 128 positioned between the gate electrode 126 and the bottom of the trench 122; an insulating region 130 which separates the carrier compensation electrode 128 from the side walls and the bottom; and a source electrode 132 which is electrically connected to the source region 120, and electrically connected to the carrier compensation electrode 128. According to this MOSFET 100, variation in the switching characteristics when the MOSFET is turned off can be reduced, even if there is variation in the charge balance around the gate.
(FR) L’invention concerne un MOSFET (100), lequel se caractérise en ce qu’il comporte: un substrat semi-conducteur (110) qui possède une zone colonne de type n (114), une zone colonne de type p (116), une zone base (118) et une zone source (120), et sur lequel est formée une structure de super jonction à l’aide de la zone colonne de type n (114) et de la zone colonne de type p (116); une tranchée (122) présentant une paroi latérale et un fond; une électrode de grille (126) formée à l’intérieur de la tranchée (122) par l’intermédiaire d'un film (124) d’isolation de grille; une électrode (128) de compensation de support située entre l’électrode de grille (126) et le fond de la tranchée (122); une zone d’isolation (130) qui sépare l’électrode (128) de compensation de support de la paroi latérale et du fond; et une électrode de source (132) reliée électriquement à la fois à la zone source (120) et à l’électrode (128) de compensation de support. Dans ce MOSFET (100) selon l’invention, même lorsque des variations apparaissent dans l’équilibre des charges proche de la grille, il est possible de réduire les variations des caractéristiques de commutation à l’état désactivé.
(JA) 本発明のMOSFET100は、n型コラム領域114及びp型コラム領域116と、ベース領域118と、ソース領域120とを有し、n型コラム領域114及びp型コラム領域116でスーパージャンクション構造が構成されている半導体基体110と、側壁及び底を有するトレンチ122と、トレンチ122内にゲート絶縁膜124を介して形成されたゲート電極126と、ゲート電極126とトレンチ122の底との間に位置するキャリア補償電極128と、側壁及び底からキャリア補償電極128を離隔させる絶縁領域130と、ソース領域120と電気的に接続されるとともにキャリア補償電極128とも電気的に接続されたソース電極132とを備えることを特徴とする。 本発明のMOSFET100によれば、ゲート周辺のチャージバランスのバラツキがあったとしても、MOSFETをターンオフしたときのスイッチング特性のバラツキを小さくすることができる。
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)