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1. (WO2018085116) PROGRAMMABLE CLOCK MONITOR
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Pub. No.: WO/2018/085116 International Application No.: PCT/US2017/058560
Publication Date: 11.05.2018 International Filing Date: 26.10.2017
Chapter 2 Demand Filed: 20.04.2018
IPC:
G06F 1/08 (2006.01) ,G06F 11/07 (2006.01) ,G06F 11/30 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
1
Details not covered by groups G06F3/-G06F13/82
04
Generating or distributing clock signals or signals derived directly therefrom
08
Clock generators with changeable or programmable clock frequency
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
11
Error detection; Error correction; Monitoring
07
Responding to the occurrence of a fault, e.g. fault tolerance
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
11
Error detection; Error correction; Monitoring
30
Monitoring
Applicants:
XILINX, INC. [US/US]; Attn: Legal Dept. 2100 Logic Drive San Jose, CA 95124, US
Inventors:
SANDERS, Lester, S.; US
KATAM, Shravanthi; US
KATTA, Abhinaya; US
PVSS, Jayaram; US
Agent:
PARANDOOSH, David, A.; US
LIU, Justin; US
HSU, Frederick; US
Priority Data:
15/340,97801.11.2016US
Title (EN) PROGRAMMABLE CLOCK MONITOR
(FR) MONITEUR D'HORLOGE PROGRAMMABLE
Abstract:
(EN) An apparatus (210) can include an interface circuit (305) configured to receive an operating parameter and a control circuit (310) coupled to the interface circuit (305) and configured to store the operating parameter. The apparatus (210) also can include a clock error detection circuit (320) coupled to the control circuit (310). The clock error detection circuit (320) can be configured to detect a clock error condition on a clock signal based upon the operating parameter and, responsive to detecting the clock error condition, generate a signal indicating an occurrence of the clock error condition.
(FR) L'invention concerne un appareil (210) qui peut comprendre un circuit d'interface (305) configuré pour recevoir un paramètre de fonctionnement et un circuit de commande (310) couplé au circuit d'interface (305) et configuré pour stocker le paramètre de fonctionnement. L'appareil (210) peut également comprendre un circuit de détection d'erreur d'horloge (320) couplé au circuit de commande (310). Le circuit de détection d'erreur d'horloge (320) peut être configuré pour détecter une condition d'erreur d'horloge sur un signal d'horloge sur la base du paramètre de fonctionnement et, en réponse à la détection de l'état d'erreur d'horloge, générer un signal indiquant une apparition de l'état d'erreur d'horloge.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)