Search International and National Patent Collections

1. (WO2018085016) METHODS OF FORMING AN ARRAY COMPRISING PAIRS OF VERTICALLY OPPOSED CAPACITORS AND ARRAYS COMPRISING PAIRS OF VERTICALLY OPPOSED CAPACITORS

Pub. No.:    WO/2018/085016    International Application No.:    PCT/US2017/056203
Publication Date: Sat May 12 01:59:59 CEST 2018 International Filing Date: Thu Oct 12 01:59:59 CEST 2017
IPC: H01L 27/06
H01L 49/02
Applicants: MICRON TECHNOLOGY, INC.
Inventors: RAMASWAMY, Durai, Vishak Nirmai
Title: METHODS OF FORMING AN ARRAY COMPRISING PAIRS OF VERTICALLY OPPOSED CAPACITORS AND ARRAYS COMPRISING PAIRS OF VERTICALLY OPPOSED CAPACITORS
Abstract:
A method of forming an array comprising pairs of vertically opposed capacitors comprises forming an upwardly-open conductive lining in individual capacitor openings in insulative-comprising material. An elevational mid- portion of individual of the conductive linings is removed to form an upper capacitor electrode lining and a lower capacitor electrode lining that are elevationally separate and spaced from one another in the individual capacitor openings. A capacitor insulator is formed radially inward of the upper and lower capacitor electrode linings in the individual capacitor openings. Conductive material is formed radially inward of the capacitor insulator in the individual capacitor openings and elevationally between the capacitor electrode linings. The conductive material is formed to comprise a shared capacitor electrode that is shared by vertically opposed capacitors in individual of the pairs of vertically opposed capacitors. Additional methods and structure independent of method are disclosed.