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1. (WO2018084957) STACKED ELECTRONICS PACKAGE AND METHOD OF MANUFACTURING THEREOF
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Pub. No.: WO/2018/084957 International Application No.: PCT/US2017/053150
Publication Date: 11.05.2018 International Filing Date: 25.09.2017
IPC:
H01L 23/538 (2006.01) ,H01L 25/16 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
52
Arrangements for conducting electric current within the device in operation from one component to another
538
the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
16
the devices being of types provided for in two or more different main groups of groups H01L27/-H01L51/139
Applicants:
GENERAL ELECTRIC COMPANY [US/US]; 1 River Road Schenectady, NY 12345, US
Inventors:
TUOMINEN, Risto, Ilkka; JP
GOWDA, Arun, Virupaksha; US
Agent:
DIMAURO, Peter, T.; US
WINTER, Catherine, J.; US
GNIBUS, Michael, M.; US
KRAMER, John, A.; US
MIDGLEY, Stephen, G.; US
Priority Data:
15/343,25904.11.2016US
Title (EN) STACKED ELECTRONICS PACKAGE AND METHOD OF MANUFACTURING THEREOF
(FR) BOÎTIER ÉLECTRONIQUE EMPILÉ ET SON PROCÉDÉ DE FABRICATION
Abstract:
(EN) An electronics package includes an insulating substrate, a first electrical component coupled to a top surface of the insulating substrate, and a second electrical component coupled to a bottom surface of the insulating substrate. A first conductor layer is formed on the bottom surface of the insulating substrate and extends through a via formed therethrough to contact a contact pad of the first electrical component, with a portion of the first conductor layer positioned between the insulating substrate and the second electrical component. A second conductor layer is formed on the top surface of the insulating substrate and extends through another via formed therethrough to electrically couple with the first conductor layer and to contact a contact pad of the second electrical component.
(FR) L'invention concerne un boîtier électronique comprenant un substrat isolant, un premier composant électrique couplé à une surface supérieure du substrat isolant, et un second composant électrique couplé à une surface inférieure du substrat isolant. Une première couche conductrice est formée sur la surface inférieure du substrat isolant et s'étend à travers un trou d'interconnexion formé à travers celle-ci pour entrer en contact avec un plot de contact du premier composant électrique, avec une partie de la première couche conductrice positionnée entre le substrat isolant et le second composant électrique. Une seconde couche conductrice est formée sur la surface supérieure du substrat isolant et s'étend à travers un autre trou d'interconnexion formé à travers celle-ci pour être couplée électriquement à la première couche conductrice et pour entrer en contact avec un plot de contact du second composant électrique.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)