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1. (WO2018083797) DIFFERENTIAL AMPLIFICATION CIRCUIT AND VOLTAGE BUFFER CIRCUIT
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Pub. No.: WO/2018/083797 International Application No.: PCT/JP2016/082966
Publication Date: 11.05.2018 International Filing Date: 07.11.2016
IPC:
H03F 3/45 (2006.01)
H ELECTRICITY
03
BASIC ELECTRONIC CIRCUITRY
F
AMPLIFIERS
3
Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
45
Differential amplifiers
Applicants:
三菱電機株式会社 MITSUBISHI ELECTRIC CORPORATION [JP/JP]; 東京都千代田区丸の内二丁目7番3号 7-3, Marunouchi 2-chome, Chiyoda-ku, Tokyo 1008310, JP
Inventors:
丸山 隆也 MARUYAMA, Takaya; JP
堤 恒次 TSUTSUMI, Koji; JP
下沢 充弘 SHIMOZAWA, Mitsuhiro; JP
Agent:
田澤 英昭 TAZAWA, Hideaki; JP
濱田 初音 HAMADA, Hatsune; JP
中島 成 NAKASHIMA, Nari; JP
坂元 辰哉 SAKAMOTO, Tatsuya; JP
辻岡 将昭 TSUJIOKA, Masaaki; JP
井上 和真 INOUE, Kazuma; JP
Priority Data:
Title (EN) DIFFERENTIAL AMPLIFICATION CIRCUIT AND VOLTAGE BUFFER CIRCUIT
(FR) CIRCUIT D'AMPLIFICATION DIFFÉRENTIEL ET CIRCUIT TAMPON DE TENSION
(JA) 差動増幅回路及び電圧バッファ回路
Abstract:
(EN) A differential amplification circuit (11) is provided with: differential input terminals (INa, INb); first and second amplification transistors (M1, M2); a common connection node (21c) electrically connected to source electrodes of the first and second amplification transistors; a constant current source (22) connected between the common connection node (21c) and a second power supply line; a voltage detector (30) which detects a common mode input voltage (Vc) from input voltages (Vinp, Vinn) applied to the differential input terminals (INa, INb); and a shunt circuit (40) which forms a current path having a conductance value corresponding to the common mode input voltage (Vc) between a first power supply line (10D) and the common connection node (21c).
(FR) Un circuit d'amplification différentiel (11) comprend : des bornes d'entrée différentielles (INa, INb) ; des premier et second transistors d'amplification (M1, M2) ; un noeud de connexion commun (21c) connecté électriquement à des électrodes de source des premier et second transistors d'amplification ; une source de courant constant (22) connectée entre le noeud de connexion commun (21c) et une seconde ligne d'alimentation électrique ; un détecteur de tension (30) qui détecte une tension d'entrée de mode commun (Vc) à partir de tensions d'entrée (Vinp, Vinn) appliquées aux bornes d'entrée différentielles (INa, INb) ; et un circuit de dérivation (40) qui forme un trajet de courant ayant une valeur de conductance correspondant à la tension d'entrée de mode commun (Vc) entre une première ligne d'alimentation électrique (10D) et le noeud de connexion commun (21c).
(JA) 差動増幅回路(11)は、差動入力端子(INa,INb)と、第1及び第2の増幅トランジスタ(M,M)と、これら第1及び第2の増幅トランジスタのソース電極と電気的に接続された共通接続ノード(21c)と、共通接続ノード(21c)と第2電源ラインとの間に接続された定電流源(22)と、差動入力端子(INa,INb)に印加された入力電圧(Vinp,Vinn)から同相入力電圧(V)を検出する電圧検出器(30)と、同相入力電圧(V)に応じたコンダクタンス値を有する電流経路を第1電源ライン(10D)と共通接続ノード(21c)との間に形成する分流回路(40)とを備える。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)