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1. (WO2018083441) MAIN PROCESSOR ERROR DETECTION USING CHECKER PROCESSORS

Pub. No.:    WO/2018/083441    International Application No.:    PCT/GB2017/053179
Publication Date: Sat May 12 01:59:59 CEST 2018 International Filing Date: Sat Oct 21 01:59:59 CEST 2017
IPC: G06F 11/16
Applicants: ARM LIMITED
THE CHANCELLOR, MASTERS AND SCHOLARS OF THE UNIVERSITY OF CAMBRIDGE
Inventors: AINSWORTH, Sam
GROCUTT, Thomas Christopher
JONES, Timothy Martin
Title: MAIN PROCESSOR ERROR DETECTION USING CHECKER PROCESSORS
Abstract:
An apparatus (2) comprises a main processor (4) to execute a main stream (30) of program instructions, two or more checker processors (20) to execute respective checker streams (34) of program instructions in parallel with each other, the checker streams corresponding to different portions (32) of the main stream executed by the main processor, and error detection circuitry (28) to detect an error when a mismatch is detected between an outcome of a given portion (32) of the main stream executed on the main processor (4) and an outcome of the corresponding checker stream (34) executed on one of the plurality of checker processors (20). This approach enables high performance main processors (4) to be checked for errors with lower circuit area and power consumption overhead than a dual-core lockstep technique.