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1. (WO2018082118) NANOWIRE NON-CRYSTALLIZED TRANSISTOR AND PREPARATION METHOD THEREFOR
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/082118 International Application No.: PCT/CN2016/106039
Publication Date: 11.05.2018 International Filing Date: 16.11.2016
IPC:
H01L 29/775 (2006.01) ,H01L 29/06 (2006.01) ,H01L 21/335 (2006.01) ,B82Y 10/00 (2011.01)
Applicants: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD[CN/CN]; Building C5 Biolake of Optics Valley,No.666 Gaoxin Avenue, East Lake High-tech Development Zone Wuhan, Hubei 430070, CN
Inventors: LIANG, Bo; CN
LI, Jun; CN
WANG, Wei; CN
Agent: CHINA WISPRO INTELLECTUAL PROPERTY LLP.; Room A806 Zhongdi Building, China University of Geosciences Base, No.8 Yuexing 3rd Road, High-Tech Industrial Estate, Nanshan District Shenzhen, Guangdong 518057, CN
Priority Data:
201610957456.603.11.2016CN
Title (EN) NANOWIRE NON-CRYSTALLIZED TRANSISTOR AND PREPARATION METHOD THEREFOR
(FR) TRANSISTOR À NANOFIL NON CRISTALLISÉ ET SON PROCÉDÉ DE PRÉPARATION
(ZH) 一种纳米线无结晶体管及其制备方法
Abstract: front page image
(EN) Disclosed in the present invention are a nanowire non-crystallized transistor and a preparation method therefor. Two ends of each of multiple nanometer channel lines in the transistor are respectively connected to a source region and a drain region, and the two ends and the source region and the drain region are made of a same doped semiconductor material. The open-state current of the transistor is increased, and the homogeneity of the transistor is improved. The multiple nanometer channel lines are disposed on an active layer in a stacked manner, thereby improving the integration of the transistor.
(FR) La présente invention concerne un transistor à nanofil non cristallisé et son procédé de préparation Deux extrémités de chacune de multiples lignes de canal nanométrique dans le transistor sont respectivement connectées à une région de source et à une région de drain, et les deux extrémités et la région de source et la région de drain sont constituées d'un même matériau semi-conducteur dopé. Le courant à l'état ouvert du transistor est augmenté, et l'homogénéité du transistor est améliorée. Les multiples lignes de canal nanométrique sont disposées sur une couche active d'une manière empilée, ce qui permet d'améliorer l'intégration du transistor.
(ZH) 本发明公开了一种纳米线无结晶体管及其制备方法,该晶体管内设置的多条纳米沟道线的各两端分别连接源区、漏区,且与源区、漏区属于同种类型掺杂的半导体材料,不仅增加了晶体管的开态电流,而且提高了晶体管的均一性,同时将该多条纳米沟道线以堆叠方式设置于有源层上,提高了晶体管的集成度。
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JP, KE, KG, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)