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1. (WO2018081705) FLEXIBLE FAN-OUT WAFER LEVEL PROCESS AND STRUCTURE

Pub. No.:    WO/2018/081705    International Application No.:    PCT/US2017/059028
Publication Date: Fri May 04 01:59:59 CEST 2018 International Filing Date: Tue Oct 31 00:59:59 CET 2017
IPC: H01L 27/12
H01L 21/56
H01L 23/532
Applicants: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
IYER, Subramanian S.
FUKUSHIMA, Takafumi
BAJWA, Adeel A.
Inventors: IYER, Subramanian S.
FUKUSHIMA, Takafumi
BAJWA, Adeel A.
Title: FLEXIBLE FAN-OUT WAFER LEVEL PROCESS AND STRUCTURE
Abstract:
A fan-out wafer level package includes: (1) a flexible substrate; (2) a semiconductor component embedded in the flexible substrate, the semiconductor component including an active surface that is exposed from the flexible substrate, the semiconductor component including a bonding pad adjacent to the active surface; (3) a stress buffer layer disposed over the flexible substrate and the semiconductor component, the stress buffer layer defining an opening exposing the bonding pad of the semiconductor component; and (4) an interconnect disposed over the stress buffer layer and including a portion extending into the opening of the stress buffer layer to electrically connect to the bonding pad of the semiconductor component.