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1. (WO2018081667) DRC PROCESSING TOOL FOR EARLY STAGE IC LAYOUT DESIGNS

Pub. No.:    WO/2018/081667    International Application No.:    PCT/US2017/058913
Publication Date: Fri May 04 01:59:59 CEST 2018 International Filing Date: Sun Oct 29 01:59:59 CEST 2017
IPC: G06F 17/50
Applicants: SYNOPSYS, INC.
Inventors: STUDDERS, John R.
Title: DRC PROCESSING TOOL FOR EARLY STAGE IC LAYOUT DESIGNS
Abstract:
A DRC tool optimized for analyzing early-stage ("dirty") IC layout designs by performing one or more of (a) automatically selectively focusing DRC processing to selected regions (i.e., layers and/or cells) of a dirty IC layout design that are most likely to provide useful error information to a user, (b) automatically selectively ordering and/or limiting rule checks performed during DRC processing to provide the user with a manageable amount of error data in a predetermined reasonable amount of time, and (c) automatically providing error data in a graphical manner using a contrasting dot to indicate the location of each rule violation, whereby relevant problem areas of the dirty IC layout design are easily identified for correction by a human user, and non-relevant areas (e.g., missing block regions) can be efficiently identified and ignored, thereby facilitating efficient modification of the IC layout design.