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1. (WO2018080712) METHOD OF FABRICATING AIR-GAP SPACER FOR N7/N5 FINFET AND BEYOND
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2018/080712 International Application No.: PCT/US2017/053802
Publication Date: 03.05.2018 International Filing Date: 27.09.2017
IPC:
H01L 29/78 (2006.01) ,H01L 29/66 (2006.01) ,H01L 29/49 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
43
characterised by the materials of which they are formed
49
Metal-insulator semiconductor electrodes
Applicants: APPLIED MATERIALS, INC.[US/US]; 3050 Bowers Avenue Santa Clara, California 95054, US
Inventors: CHANG, Chih-Yang; US
HUNG, Raymond Hoiman; US
SATO, Tatsuya E.; US
KIM, Nam Sung; US
SUN, Shiyu; US
WOOD, Bingxi Sun; US
Agent: PATTERSON, B. Todd; US
TABOADA, Keith; US
Priority Data:
15/490,59318.04.2017US
62/414,50128.10.2016US
Title (EN) METHOD OF FABRICATING AIR-GAP SPACER FOR N7/N5 FINFET AND BEYOND
(FR) PROCÉDÉ DE FABRICATION D'ESPACEUR D'ENTREFER POUR FINFET N7/N5 ET AU-DELÀ
Abstract:
(EN) Embodiments disclosed herein relate to an improved transistor with reduced parasitic capacitance. In one embodiment, the transistor device includes a three-dimensional fin structure protruding from a surface of a substrate, the three-dimensional fin structure comprising a top surface and two opposing sidewalls, a first insulating layer formed on the two opposing sidewalls of the three-dimension fin structure, a sacrificial spacer layer conformally formed on the first insulating layer, wherein the sacrificial spacer layer comprises an aluminum oxide based material or a titanium nitride based material, and a second insulating layer conformally formed on the sacrificial spacer layer.
(FR) Des modes de réalisation de la présente invention concernent un transistor amélioré à capacité parasite réduite. Dans un mode de réalisation, le dispositif de transistor comprend une structure d'ailette tridimensionnelle faisant saillie à partir d'une surface d'un substrat, la structure d'ailette tridimensionnelle comprenant une surface supérieure et deux parois latérales opposées, une première couche isolante formée sur les deux parois latérales opposées de la structure d'ailette tridimensionnelle, une couche d'espacement sacrificielle formée de manière conforme sur la première couche isolante, la couche d'espacement sacrificielle comprenant un matériau à base d'oxyde d'aluminium ou un matériau à base de nitrure de titane, et une seconde couche isolante formée de manière conforme sur la couche d'espacement sacrificielle.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)