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1. (WO2018080643) 3D CHIP ASSEMBLIES USING STACKED LEADFRAMES

Pub. No.:    WO/2018/080643    International Application No.:    PCT/US2017/050548
Publication Date: Fri May 04 01:59:59 CEST 2018 International Filing Date: Fri Sep 08 01:59:59 CEST 2017
IPC: H01L 25/07
H01L 25/065
H01L 23/00
H01L 23/498
Applicants: INTEL CORPORATION
Inventors: RUNYAN, Cory A.
PON, Florence R.
Title: 3D CHIP ASSEMBLIES USING STACKED LEADFRAMES
Abstract:
A stacked-chip assembly including a plurality of IC chips or die that are stacked, and a plurality of stacked leads. Leads from separate leadframes may be bonded together so as to tie corresponding metal features of the various chips to a same ground, signal, or power rail. Each leadframe may include a center paddle, which is disposed between two chips in the stack. The center paddle may function as one or more of a thermal conduit and common electrical rail (e.g., ground). The leadframes may be employed without the use of any bond wires with leads bonded directly to bond pads of the chips. A first IC chip may be mounted to a base leadframe and subsequent die-attach leadframes and IC chips are stacked upon the first IC chip and base leadframe. The die-attach leadframes may be iteratively bonded to an underlying leadframe and the bonded stacked leads stamped out of their respective leadframe sheets.